If the Run in Standby (RUNSTDBY) bit in the Control A (DACn.CTRLA) register is
written to ‘1’, the DAC will continue to operate in Standby sleep mode.
If the RUNSTDBY bit is zero, the DAC will stop the conversion in Standby sleep mode.
If the conversion is stopped in Standby sleep mode, the DAC and the output
buffer are disabled to reduce power consumption. When the device is exiting Standby
sleep mode, the DAC and the output buffer (if the OUTEN bit in the Control A
(DACn.CTRLA) register is written to ‘1’) are enabled again. Therefore,
a start-up time is required before a new conversion is initiated.
In Power-Down sleep mode, the DAC and the output buffer are disabled to reduce power consumption.