Follow these steps to issue a chip erase:
- 1.Enter the Chip Erase key by using
the
KEY instruction. See the Key Activation Signatures
table in the Enabling of Key Protected Interfaces section for the
CHIPERASE signature.
- 2.Optional: Read the Chip
Erase (CHIPER) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS) register to see
that the key is successfully activated.
- 3.Write the signature to the Reset
Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ) register.
This will issue a System Reset.
- 4.Write
0x00 to
the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System
Reset.
- 5.Read the NVM Lock Status
(LOCKSTATUS) bit from the ASI System Status (UPDI.ASI_SYS_STATUS) register.
- 6.The chip erase is done when the
LOCKSTATUS bit is ‘
0’. If the LOCKSTATUS bit is
‘1’, return to step 5.
- 7.Check the Chip Erase Key Failed
(ERASEFAIL) bit in the ASI System Status (UPDI.ASI_SYS_STATUS) register to
verify if the chip erase was successful.
- 8.If the ERASEFAIL bit is
‘
0’, the chip erase was successful.
After a successful chip erase, the lock bits will be cleared, and the UPDI
will have full access to the system. Until the lock bits are cleared, the UPDI cannot
access the system bus, and only CS-space operations can be performed.
CAUTION: During chip erase, the
BOD is forced in ON state by writing to the Active (ACTIVE) bit field from the Control A
(BOD.CTRLA) register and uses the BOD Level (LVL) bit field from the BOD Configuration
(FUSE.BODCFG) fuse and the BOD Level (LVL) bit field from the Control B (BOD.CTRLB)
register. If the supply voltage VDD is below that threshold level, the device
is unavailable until VDD is increased adequately. See the BOD section
for more details.