The EEPROM Erase/Write (EEERWR) mode enables the EEPROM array for the erase operation directly followed by a write operation. Several erase/writes can be done while the EEERWR mode is enabled in the NVMCTRL.CTRLA register. When the EEERWR mode is enabled, writes with the ST* instructions are performed one byte at a time.
When writing/erasing the EEPROM, the CPU will continue executing code.
If a new load or store instruction is started before the erase/write is completed, the CPU will be halted.