In Two Ramp mode, the TCD counter counts up until it reaches the CMPACLR
value, then it resets and counts up until it reaches the CMPBCLR value. Then, the TCD
cycle is completed, and the counter restarts from 0x000, beginning a
new TCD cycle. The TCD cycle period is given by:
In the figure above, CMPASET < CMPACLR and CMPBSET < CMPBCLR. This causes the outputs to go high. There are no restrictions on the CMPASET and CMPACLR compared to the CMPBSET and CMPBCLR values.
In Two Ramp mode, it is not possible to get overlapping outputs without using the override feature. Even if CMPASET/CMPBSET > CMPACLR/CMPBCLR, the counter resets at CMPACLR/CMPBCLR and will never reach CMPASET/CMPBSET.