The input selection for the ADC is controlled by the MUXPOS and MUXNEG bit fields in the ADCn.MUXPOS and ADCn.MUXNEG registers, respectively. If the ADC is running single-ended conversions, only MUXPOS is used, while both are used in differential conversions.
The MUXPOS bit field of the ADCn.MUXPOS register and the MUXNEG bit field of the ADCn.MUXNEG register are buffered through a temporary register. This ensures that the input selection only comes into effect at a safe point during the conversion. The channel selections are continuously updated until a conversion is started.
Once the conversion starts, the channel selections are locked to ensure
sufficient sampling time for the ADC. The continuous updating of input channel selection
resumes in the last CLK_ADC clock cycle before the conversion completes. The next
conversion starts on the following rising CLK_ADC clock edge after the STCONV bit is
written to ‘1’.