The UPDI pin has an internal pull-up resistor, and by driving the UPDI pin low for more than 200 ns, a connected programmer will initiate the start-up sequence.
The negative edge transition will cause an edge detector (located in the high-voltage domain if it is in a multi-voltage system) to start driving the UPDI pin low, so when the programmer releases the line, it will stay low until the requested UPDI oscillator is ready. The expected arrival time for the clock will depend on the oscillator implementation regarding the accuracy, overshoot, and readout of the oscillator calibration. For a multi-voltage system, the line will be driven low until the regulator is at the correct level, and the system is powered up with the selected oscillator ready and stable. The programmer must poll the UPDI pin after releasing it the first time to detect when the pin transitions to high again. This transition means that the edge detector has released the pin (pull-up), and the UPDI can receive a SYNCH character. Upon successful detection of the SYNCH character, the UPDI is enabled and will prepare for the reception of the first instruction.
The enable transmission sequence is shown in Figure 1, where the active driving periods for the programmer and edge detector are included. The “UPDI pin” waveform shows the pin value at any given time.
The delay given for the edge detector active drive period is a typical start-up time waiting for 256 cycles on a 32 MHz oscillator + the calibration readout. Refer to the Electrical Characteristics section for details on the expected start-up times.
To avoid the UPDI from staying enabled if an accidental trigger of the edge detector happens, the UPDI will automatically disable itself and lower its clock request. See the Disable During Start-Up section for more details.