Register Synchronization Categories

Most of the I/O registers need to be synchronized to the TCD core clock domain, which is done differently for different register categories.

Table 1. Categorization of Registers
Enable and Command Registers	Double-Buffered Registers	Static Registers	Read-Only Registers	Normal I/O Registers
TCDn.CTRLA (ENABLE bit)	TCDn.DLYCTRL	TCDn.CTRLA⁽¹⁾ (all bits except ENABLE bit)	TCDn.STATUS	TCDn.INTCTRL
TCDn.CTRLE	TCDn.DLYVAL	TCDn.CTRLB	TCDn.CAPTUREA	TCDn.INTFLAGS
	TCDn.DITCTRL	TCDn.CTRLC	TCDn.CAPTUREB
	TCDn.DITVAL	TCDn.CTRLD
	TCDn.DBGCTRL	TCDn.EVCTRLA
	TCDn.CMPASET	TCDn.EVCTRLB
	TCDn.CMPACLR	TCDn.INPUTCTRLA
	TCDn.CMPBSET	TCDn.INPUTCTRLB
	TCDn.CMPBCLR	TCDn.FAULTCTRL⁽²⁾

Notes:

1.The bits in the Control A (TCDn.CTRLA) register are enable-protected, except the ENABLE bit. They can only be written when ENABLE is written to ‘0’ first.
2.This register is protected by the Configuration Change Protection Mechanism, requiring a timed write procedure for changing its value settings.

Enable and Command Registers

Because of the synchronization between the clock domains, it is only possible to change the ENABLE bit in the Control A (TCDn.CTRLA) register, while the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register is ‘1’.

The Control E (TCDn.CTRLE) register is automatically synchronized to the TCD core domain when the TCD is enabled and as long as no synchronization is ongoing already. Check if the Command Ready (CCMDRDY) bit in the TCDn.STATUS register is ‘1’ to ensure that it is possible to issue a new command. The TCDn.CTRLE is a strobe register that will clear itself when the command is sent.

Double-Buffered Registers

The double-buffered registers can be updated in normal I/O writes while the TCD is enabled, and no synchronization between the two clock domains is ongoing. Check that the CMDRDY bit in the TCDn.STATUS register is ‘1’ to ensure that it is possible to update the double-buffered registers. The values will be synchronized to the TCD core domain when a synchronization command is sent or when the TCD is enabled.

Table 2. Issuing Synchronization Command
Synchronization Issuing Bit	Double Register Update
CTRLC.AUPDATE	Every time the TCDn.CMPBCLRH register is written, the synchronization occurs at the end of the TCD cycle
CTRLE.SYNC ⁽¹⁾	Occurs once, as soon as the SYNC bit is synchronized with the TDC domain
CTRLE.SYNCEOC ⁽¹⁾	Occurs once at the end of the next TCD cycle

Note:

1.If the synchronization is already ongoing, the action has no effect.

Static Registers

Static registers cannot be updated while the TCD is enabled. Therefore, these registers must be configured before enabling the TCD. To see if the TCD is enabled, check if the ENABLE bit in the TCDn.CTRLA register is read as ‘1’.

Normal I/O and Read-Only Registers

Normal I/O and read-only registers are not constrained by any synchronization between the domains. The read-only registers inform about synchronization status and values synchronized from the core domain.