Conversion Timing

A normal conversion takes place in the following order:
  1. 1.Write a ‘1’ to the STCONV bit in the Command (ADCn.COMMAND) register.
  2. 2.Start-up for maximum 2 CLK_PER cycles.
  3. 3. Sample-and-hold for 2 CLK_ADC cycles.
  4. 4.Conversion for 13.5 CLK_ADC cycles.
  5. 5.Result formatting for 2 CLK_PER cycles.

When a conversion is complete, the result is available in the Result (ADCn.RES) register, and the Result Ready (RESRDY) interrupt flag is set in the Interrupt Flags (ADCn.INTFLAGS) register.

Parent topic: Operation