Contents

Introduction AVR DA Family Overview 2.1. Memory Overview 2.2. Peripheral Overview Features 4. Block Diagram 5. Pinout 5.1. 28-Pin SPDIP, SSOP and SOIC 5.2. 32-Pin VQFN and TQFP 5.3. 48-Pin VQFN and TQFP 6. I/O Multiplexing and Considerations 6.1. I/O Multiplexing 7. Hardware Guidelines 7.1. General Guidelines 7.1.1. Special Consideration for VQFN Packages 7.2. Connection for Power Supply 7.2.1. Digital Power Supply 7.3. Connection for RESET 7.4. Connection for UPDI Programming 7.5. Connecting External Crystal Oscillators 7.6. Connection for External Voltage Reference 8. Conventions 8.1. Numerical Notation 8.2. Memory Size and Type 8.3. Frequency and Time 8.4. Registers and Bits 8.4.1. Addressing Registers from Header Files 8.5. ADC Parameter Definitions 9. AVR CPU 9.1. Features 9.2. Overview 9.3. Architecture 9.3.1. Arithmetic Logic Unit (ALU) 9.3.1.1. Hardware Multiplier 9.4. Functional Description 9.4.1. Program Flow 9.4.2. Instruction Execution Timing 9.4.3. Status Register 9.4.4. Stack and Stack Pointer 9.4.5. Register File 9.4.5.1. The X-, Y-, and Z-Registers 9.4.5.2. Extended Pointers 9.4.6. Configuration Change Protection (CCP) 9.4.6.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 9.4.6.2. Sequence for Execution of Self-Programming 9.4.7. On-Chip Debug Capabilities 9.5. Register Summary 9.6. Register Description 9.6.1. CCP 9.6.2. SP 9.6.3. SREG 9.6.4. RAMPZ 10. Memories 10.1. Overview 10.2. Memory Map 10.3. In-System Reprogrammable Flash Program Memory 10.4. SRAM Data Memory 10.5. EEPROM Data Memory 10.6. SIGROW - Signature Row 10.6.1. Signature Row Summary 10.6.2. Signature Row Description 10.6.2.1. Device ID 10.6.2.2. Temperature Sensor Calibration n 10.6.2.3. Serial Number Byte n 10.7. USERROW - User Row 10.8. FUSE - Configuration and User Fuses 10.8.1. Fuse Summary 10.8.2. Fuse Description 10.8.2.1. Watchdog Configuration 10.8.2.2. Brown-out Detector Configuration 10.8.2.3. Oscillator Configuration 10.8.2.4. System Configuration 0 10.8.2.5. System Configuration 1 10.8.2.6. Code Size 10.8.2.7. Boot Size 10.9. LOCK - Memory Sections Access Protection 10.9.1. Lock Summary 10.9.2. Lock Description 10.9.2.1. Lock Key 10.10. I/O Memory 10.10.1. Single-Cycle I/O Registers 10.10.2. Extended I/O Registers 10.10.3. Accessing 16-bit Registers 10.10.4. Accessing 24-Bit Registers 11. Peripherals and Architecture 11.1. Peripheral Address Map 11.2. Interrupt Vector Mapping 11.3. SYSCFG - System Configuration 11.3.1. Register Summary 11.3.2. Register Description 11.3.2.1. Device Revision ID Register 12. GPR - General Purpose Registers 12.1. Register Summary 12.2. Register Description 12.2.1. General Purpose Register n 13. NVMCTRL - Nonvolatile Memory Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.3. Functional Description 13.3.1. Memory Organization 13.3.1.1. Flash 13.3.1.2. EEPROM 13.3.1.3. Signature Row 13.3.1.4. User Row 13.3.1.5. Fuses 13.3.2. Memory Access 13.3.2.1. Read 13.3.2.2. Programming 13.3.2.3. Command Modes 13.3.2.3.1. Flash Write Mode 13.3.2.3.2. Flash Page Erase Mode 13.3.2.3.3. Flash Multi-Page Erase Mode 13.3.2.3.4. EEPROM Write Mode 13.3.2.3.5. EEPROM Erase/Write Mode 13.3.2.3.6. EEPROM Byte Erase Mode 13.3.2.3.7. EEPROM Multi-Byte Erase Mode 13.3.2.3.8. Chip Erase Command 13.3.2.3.9. EEPROM Erase Command 13.3.3. Preventing Flash/EEPROM Corruption 13.3.4. Interrupts 13.3.5. Sleep Mode Operation 13.3.6. Configuration Change Protection 13.4. Register Summary 13.5. Register Description 13.5.1. Control A 13.5.2. Control B 13.5.3. Status 13.5.4. Interrupt Control 13.5.5. Interrupt Flags 13.5.6. Data 13.5.7. Address 14. CLKCTRL - Clock Controller 14.1. Features 14.2. Overview 14.2.1. Block Diagram - CLKCTRL 14.2.2. Signal Description 14.3. Functional Description 14.3.1. Main Clock Selection and Prescaler 14.3.2. Main Clock After Reset 14.3.3. Clock Sources 14.3.3.1. Internal Oscillators 14.3.3.1.1. Internal High-Frequency Oscillator (OSCHF) 14.3.3.1.2. 32.768 kHz Oscillator (OSC32K) 14.3.3.2. External Clock Sources 14.3.3.2.1. 32.768 kHz Crystal Oscillator (XOSC32K) 14.3.3.2.2. External Clock (EXTCLK) 14.3.4. Phase-Locked Loop (PLL) 14.3.5. Manual Tuning and Auto-Tune 14.3.6. Sleep Mode Operation 14.3.7. Configuration Change Protection 14.4. Register Summary 14.5. Register Description 14.5.1. Main Clock Control A 14.5.2. Main Clock Control B 14.5.3. Main Clock Lock 14.5.4. Main Clock Status 14.5.5. Internal High-Frequency Oscillator Control A 14.5.6. Internal High-Frequency Oscillator Frequency Tune 14.5.7. PLL Control A 14.5.8. 32.768 kHz Oscillator Control A 14.5.9. 32.768 kHz Crystal Oscillator Control A 15. SLPCTRL - Sleep Controller 15.1. Features 15.2. Overview 15.2.1. Block Diagram 15.3. Functional Description 15.3.1. Initialization 15.3.2. Voltage Regulator Configuration 15.3.3. Operation 15.3.3.1. Sleep Modes 15.3.3.2. Wake-Up Time 15.3.4. Debug Operation 15.3.5. Configuration Change Protection 15.4. Register Summary 15.5. Register Description 15.5.1. Control A 15.5.2. Voltage Regulator Control Register 16. RSTCTRL - Reset Controller 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.2.2. Signal Description 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Reset Sources 16.3.2.1.1. Power-on Reset (POR) 16.3.2.1.2. Brown-out Detector (BOD) Reset 16.3.2.1.3. External Reset (RESET) 16.3.2.1.4. Watchdog Timer (WDT) Reset 16.3.2.1.5. Software Reset (SWRST) 16.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset 16.3.2.1.7. Domains Affected By Reset 16.3.2.2. Reset Time 16.3.3. Sleep Mode Operation 16.3.4. Configuration Change Protection 16.4. Register Summary 16.5. Register Description 16.5.1. Reset Flag Register 16.5.2. Software Reset Register 17. CPUINT - CPU Interrupt Controller 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.3. Functional Description 17.3.1. Initialization 17.3.2. Operation 17.3.2.1. Enabling, Disabling and Resetting 17.3.2.2. Interrupt Vector Locations 17.3.2.3. Interrupt Response Time 17.3.2.4. Interrupt Priority 17.3.2.4.1. Non-Maskable Interrupts 17.3.2.4.2. High-Priority Interrupt 17.3.2.4.3. Normal-Priority Interrupts 17.3.2.4.3.1. Static Scheduling 17.3.2.4.3.2. Modified Static Scheduling 17.3.2.4.3.3. Round Robin Scheduling 17.3.2.5. Compact Vector Table 17.3.3. Debug Operation 17.3.4. Configuration Change Protection 17.4. Register Summary 17.5. Register Description 17.5.1. Control A 17.5.2. Status 17.5.3. Interrupt Priority Level 0 17.5.4. Interrupt Vector with Priority Level 1 18. EVSYS - Event System 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.2.2. Signal Description 18.3. Functional Description 18.3.1. Initialization 18.3.2. Operation 18.3.2.1. Event User Multiplexer Setup 18.3.2.2. Event System Channel 18.3.2.3. Event Generators 18.3.2.4. Event Users 18.3.2.5. Synchronization 18.3.2.6. Software Event 18.3.3. Sleep Mode Operation 18.3.4. Debug Operation 18.4. Register Summary 18.5. Register Description 18.5.1. Software Events 18.5.2. Channel n Generator Selection 18.5.3. User Channel MUX 19. PORTMUX - Port Multiplexer 19.1. Overview 19.2. Register Summary 19.3. Register Description 19.3.1. EVSYS Pin Position 19.3.2. CCL LUTn Pin Position 19.3.3. USARTn Pin Position 19.3.4. USARTn Pin Position 19.3.5. SPIn Pin Position 19.3.6. TWIn Pin Position 19.3.7. TCAn Pin Position 19.3.8. TCBn Pin Position 19.3.9. TCDn Pin Position 19.3.10. ACn Pin Position 19.3.11. ZCDn Pin Position 20. PORT - I/O Pin Configuration 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.2.2. Signal Description 20.3. Functional Description 20.3.1. Initialization 20.3.2. Operation 20.3.2.1. Basic Functions 20.3.2.2. Port Configuration 20.3.2.3. Pin Configuration 20.3.2.4. Multi-Pin Configuration 20.3.2.5. Virtual Ports 20.3.2.6. Peripheral Override 20.3.3. Interrupts 20.3.3.1. Asynchronous Sensing Pin Properties 20.3.4. Events 20.3.5. Sleep Mode Operation 20.3.6. Debug Operation 20.4. Register Summary - PORTx 20.5. Register Description - PORTx 20.5.1. Data Direction 20.5.2. Data Direction Set 20.5.3. Data Direction Clear 20.5.4. Data Direction Toggle 20.5.5. Output Value 20.5.6. Output Value Set 20.5.7. Output Value Clear 20.5.8. Output Value Toggle 20.5.9. Input Value 20.5.10. Interrupt Flags 20.5.11. Port Control 20.5.12. Multi-Pin Configuration 20.5.13. Multi-Pin Control Update Mask 20.5.14. Multi-Pin Control Set Mask 20.5.15. Multi-Pin Control Clear Mask 20.5.16. Pin n Control 20.6. Register Summary - VPORTx 20.7. Register Description - VPORTx 20.7.1. Data Direction 20.7.2. Output Value 20.7.3. Input Value 20.7.4. Interrupt Flags 21. BOD - Brown-out Detector 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.3. Functional Description 21.3.1. Initialization 21.3.2. Interrupts 21.3.3. Sleep Mode Operation 21.3.4. Configuration Change Protection 21.4. Register Summary 21.5. Register Description 21.5.1. Control A 21.5.2. Control B 21.5.3. VLM Control 21.5.4. Interrupt Control 21.5.5. VLM Interrupt Flags 21.5.6. VLM Status 22. VREF - Voltage Reference 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.3. Functional Description 22.3.1. Initialization 22.4. Register Summary 22.5. Register Description 22.5.1. ADC0 Reference 22.5.2. DAC0 Reference 22.5.3. Analog Comparator Reference 23. WDT - Watchdog Timer 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.3. Functional Description 23.3.1. Initialization 23.3.2. Clocks 23.3.3. Operation 23.3.3.1. Normal Mode 23.3.3.2. Window Mode 23.3.3.3. Preventing Unintentional Changes 23.3.4. Sleep Mode Operation 23.3.5. Debug Operation 23.3.6. Synchronization 23.3.7. Configuration Change Protection 23.4. Register Summary 23.5. Register Description 23.5.1. Control A 23.5.2. Status 24. TCA - 16-bit Timer/Counter Type A 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.2.2. Signal Description 24.3. Functional Description 24.3.1. Definitions 24.3.2. Initialization 24.3.3. Operation 24.3.3.1. Normal Operation 24.3.3.2. Double Buffering 24.3.3.3. Changing the Period 24.3.3.4. Compare Channel 24.3.3.4.1. Waveform Generation 24.3.3.4.2. Frequency (FRQ) Waveform Generation 24.3.3.4.3. Single-Slope PWM Generation 24.3.3.4.4. Dual-Slope PWM 24.3.3.4.5. Port Override for Waveform Generation 24.3.3.5. Timer/Counter Commands 24.3.3.6. Split Mode - Two 8-Bit Timer/Counters 24.3.4. Events 24.3.5. Interrupts 24.3.6. Sleep Mode Operation 24.4. Register Summary - Normal Mode 24.5. Register Description - Normal Mode 24.5.1. Control A - Normal Mode 24.5.2. Control B - Normal Mode 24.5.3. Control C - Normal Mode 24.5.4. Control D - Normal Mode 24.5.5. Control Register E Clear - Normal Mode 24.5.6. Control Register E Set - Normal Mode 24.5.7. Control Register F Clear 24.5.8. Control Register F Set 24.5.9. Event Control 24.5.10. Interrupt Control Register - Normal Mode 24.5.11. Interrupt Flag Register - Normal Mode 24.5.12. Debug Control Register - Normal Mode 24.5.13. Temporary Bits for 16-Bit Access 24.5.14. Counter Register - Normal Mode 24.5.15. Period Register - Normal Mode 24.5.16. Compare n Register - Normal Mode 24.5.17. Period Buffer Register 24.5.18. Compare n Buffer Register 24.6. Register Summary - Split Mode 24.7. Register Description - Split Mode 24.7.1. Control A - Split Mode 24.7.2. Control B - Split Mode 24.7.3. Control C - Split Mode 24.7.4. Control D - Split Mode 24.7.5. Control Register E Clear - Split Mode 24.7.6. Control Register E Set - Split Mode 24.7.7. Interrupt Control Register - Split Mode 24.7.8. Interrupt Flag Register - Split Mode 24.7.9. Debug Control Register - Split Mode 24.7.10. Low Byte Timer Counter Register - Split Mode 24.7.11. High Byte Timer Counter Register - Split Mode 24.7.12. Low Byte Timer Period Register - Split Mode 24.7.13. High Byte Period Register - Split Mode 24.7.14. Compare Register n For Low Byte Timer - Split Mode 24.7.15. High Byte Compare Register n - Split Mode 25. TCB - 16-Bit Timer/Counter Type B 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Definitions 25.3.2. Initialization 25.3.3. Operation 25.3.3.1. Modes 25.3.3.1.1. Periodic Interrupt Mode 25.3.3.1.2. Time-Out Check Mode 25.3.3.1.3. Input Capture on Event Mode 25.3.3.1.4. Input Capture Frequency Measurement Mode 25.3.3.1.5. Input Capture Pulse-Width Measurement Mode 25.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 25.3.3.1.7. Single-Shot Mode 25.3.3.1.8. 8-Bit PWM Mode 25.3.3.2. Output 25.3.3.3. 32-Bit Input Capture 25.3.3.4. Noise Canceler 25.3.3.5. Synchronized with Timer/Counter Type A 25.3.4. Events 25.3.5. Interrupts 25.3.6. Sleep Mode Operation 25.4. Register Summary 25.5. Register Description 25.5.1. Control A 25.5.2. Control B 25.5.3. Event Control 25.5.4. Interrupt Control 25.5.5. Interrupt Flags 25.5.6. Status 25.5.7. Debug Control 25.5.8. Temporary Value 25.5.9. Count 25.5.10. Capture/Compare 26. TCD - 12-Bit Timer/Counter Type D 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.2.2. Signal Description 26.3. Functional Description 26.3.1. Definitions 26.3.2. Initialization 26.3.3. Operation 26.3.3.1. Register Synchronization Categories 26.3.3.2. Waveform Generation Modes 26.3.3.2.1. One Ramp Mode 26.3.3.2.2. Two Ramp Mode 26.3.3.2.3. Four Ramp Mode 26.3.3.2.4. Dual Slope Mode 26.3.3.3. Disabling TCD 26.3.3.4. TCD Inputs 26.3.3.4.1. Input Blanking 26.3.3.4.2. Digital Filter 26.3.3.4.3. Asynchronous Event Detection 26.3.3.4.4. Software Commands 26.3.3.4.5. Input Modes 26.3.3.4.5.1. Input Modes Validity 26.3.3.4.5.2. Input Mode 0: Input Has No Action 26.3.3.4.5.3. Input Mode 1: Stop Output, Jump to the Opposite Compare Cycle, and Wait 26.3.3.4.5.4. Input Mode 2: Stop Output, Execute Opposite Compare Cycle, and Wait 26.3.3.4.5.5. Input Mode 3: Stop Output, Execute Opposite Compare Cycle while Fault Active 26.3.3.4.5.6. Input Mode 4: Stop all Outputs, Maintain Frequency 26.3.3.4.5.7. Input Mode 5: Stop all Outputs, Execute Dead-Time while Fault Active 26.3.3.4.5.8. Input Mode 6: Stop All Outputs, Jump to Next Compare Cycle, and Wait 26.3.3.4.5.9. Input Mode 7: Stop all Outputs, Wait for Software Action 26.3.3.4.5.10. Input Mode 8: Stop Output on Edge, Jump to Next Compare Cycle 26.3.3.4.5.11. Input Mode 9: Stop Output on Edge, Maintain Frequency 26.3.3.4.5.12. Input Mode 10: Stop Output at Level, Maintain Frequency 26.3.3.4.5.13. Input Mode Summary 26.3.3.5. Dithering 26.3.3.6. TCD Counter Capture 26.3.3.7. Output Control 26.3.4. Events 26.3.4.1. Programmable Output Events 26.3.5. Interrupts 26.3.6. Sleep Mode Operation 26.3.7. Debug Operation 26.3.8. Configuration Change Protection 26.4. Register Summary 26.5. Register Description 26.5.1. Control A 26.5.2. Control B 26.5.3. Control C 26.5.4. Control D 26.5.5. Control E 26.5.6. Event Control A 26.5.7. Event Control B 26.5.8. Interrupt Control 26.5.9. Interrupt Flags 26.5.10. Status 26.5.11. Input Control A 26.5.12. Input Control B 26.5.13. Fault Control 26.5.14. Delay Control 26.5.15. Delay Value 26.5.16. Dither Control 26.5.17. Dither Value 26.5.18. Debug Control 26.5.19. Capture A 26.5.20. Capture B 26.5.21. Compare Set A 26.5.22. Compare Set B 26.5.23. Compare Clear A 26.5.24. Compare Clear B 27. RTC - Real-Time Counter 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.3. Clocks 27.4. RTC Functional Description 27.4.1. Initialization 27.4.1.1. Configure the Clock CLK_RTC 27.4.1.2. Configure RTC 27.4.2. Operation - RTC 27.4.2.1. Enabling and Disabling 27.5. PIT Functional Description 27.5.1. Initialization 27.5.2. Operation - PIT 27.5.2.1. Enabling and Disabling 27.5.2.2. PIT Interrupt Timing 27.6. Crystal Error Correction 27.7. Events 27.8. Interrupts 27.9. Sleep Mode Operation 27.10. Synchronization 27.11. Debug Operation 27.12. Register Summary 27.13. Register Description 27.13.1. Control A 27.13.2. Status 27.13.3. Interrupt Control 27.13.4. Interrupt Flag 27.13.5. Temporary 27.13.6. Debug Control 27.13.7. Crystal Frequency Calibration 27.13.8. Clock Selection 27.13.9. Count 27.13.10. Period 27.13.11. Compare 27.13.12. Periodic Interrupt Timer Control A 27.13.13. Periodic Interrupt Timer Status 27.13.14. PIT Interrupt Control 27.13.15. PIT Interrupt Flag 27.13.16. Periodic Interrupt Timer Debug Control 28. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Frame Formats 28.3.2.2. Clock Generation 28.3.2.2.1. The Fractional Baud Rate Generator 28.3.2.3. Data Transmission 28.3.2.3.1. Disabling the Transmitter 28.3.2.4. Data Reception 28.3.2.4.1. Receiver Error Flags 28.3.2.4.2. Disabling the Receiver 28.3.2.4.3. Flushing the Receive Buffer 28.3.3. Communication Modes 28.3.3.1. Synchronous Operation 28.3.3.1.1. Clock Operation 28.3.3.1.2. External Clock Limitations 28.3.3.1.3. USART in Host SPI Mode 28.3.3.1.3.1. Frame Formats 28.3.3.1.3.2. Clock Generation 28.3.3.1.3.3. Data Transmission 28.3.3.1.3.4. Data Reception 28.3.3.1.3.5. USART in Host SPI Mode vs. SPI 28.3.3.2. Asynchronous Operation 28.3.3.2.1. Clock Recovery 28.3.3.2.2. Data Recovery 28.3.3.2.3. Error Tolerance 28.3.3.2.4. Double-Speed Operation 28.3.3.2.5. Auto-Baud 28.3.3.2.6. Half-Duplex Operation 28.3.3.2.6.1. One-Wire Mode 28.3.3.2.6.2. RS-485 Mode 28.3.3.2.7. IRCOM Mode of Operation 28.3.4. Additional Features 28.3.4.1. Parity 28.3.4.2. Start-of-Frame Detection 28.3.4.3. Multiprocessor Communication 28.3.4.3.1. Using Multiprocessor Communication 28.3.5. Events 28.3.6. Interrupts 28.4. Register Summary 28.5. Register Description 28.5.1. Receiver Data Register Low Byte 28.5.2. Receiver Data Register High Byte 28.5.3. Transmit Data Register Low Byte 28.5.4. Transmit Data Register High Byte 28.5.5. USART Status Register 28.5.6. Control A 28.5.7. Control B 28.5.8. Control C - Normal Mode 28.5.9. Control C - Host SPI Mode 28.5.10. Baud Register 28.5.11. Control D 28.5.12. Debug Control Register 28.5.13. IrDA Control Register 28.5.14. IRCOM Transmitter Pulse Length Control Register 28.5.15. IRCOM Receiver Pulse Length Control Register 29. SPI - Serial Peripheral Interface 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.3. Functional Description 29.3.1. Initialization 29.3.2. Operation 29.3.2.1. Host Mode Operation 29.3.2.1.1. Normal Mode 29.3.2.1.2. Buffer Mode 29.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support 29.3.2.2. Client Mode 29.3.2.2.1. Normal Mode 29.3.2.2.2. Buffer Mode 29.3.2.2.3. SS Pin Functionality in Client Mode 29.3.2.3. Data Modes 29.3.2.4. Events 29.3.2.5. Interrupts 29.4. Register Summary 29.5. Register Description 29.5.1. Control A 29.5.2. Control B 29.5.3. Interrupt Control 29.5.4. Interrupt Flags - Normal Mode 29.5.5. Interrupt Flags - Buffer Mode 29.5.6. Data 30. TWI - Two-Wire Interface 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Signal Description 30.3. Functional Description 30.3.1. General TWI Bus Concepts 30.3.2. TWI Basic Operation 30.3.2.1. Initialization 30.3.2.1.1. Host Initialization 30.3.2.1.2. Client Initialization 30.3.2.2. TWI Host Operation 30.3.2.2.1. Clock Generation 30.3.2.2.2. TWI Bus State Logic 30.3.2.2.3. Transmitting Address Packets 30.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 30.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 30.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client 30.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error 30.3.2.2.4. Transmitting Data Packets 30.3.2.2.5. Receiving Data Packets 30.3.2.3. TWI Client Operation 30.3.2.3.1. Receiving Address Packets 30.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 30.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 30.3.2.3.1.3. Case S3: Stop Condition Received 30.3.2.3.1.4. Case S4: Collision 30.3.2.3.2. Receiving Data Packets 30.3.2.3.3. Transmitting Data Packets 30.3.3. Additional Features 30.3.3.1. SMBus 30.3.3.2. Multi-Host 30.3.3.3. Smart Mode 30.3.3.4. Dual Mode 30.3.3.5. Quick Command Mode 30.3.3.6. 10-Bit Address 30.3.4. Interrupts 30.3.5. Sleep Mode Operation 30.3.6. Debug Operation 30.4. Register Summary 30.5. Register Description 30.5.1. Control A 30.5.2. Dual Mode Control Configuration 30.5.3. Debug Control 30.5.4. Host Control A 30.5.5. Host Control B 30.5.6. Host Status 30.5.7. Host Baud Rate 30.5.8. Host Address 30.5.9. Host Data 30.5.10. Client Control A 30.5.11. Client Control B 30.5.12. Client Status 30.5.13. Client Address 30.5.14. Client Data 30.5.15. Client Address Mask 31. CRCSCAN - Cyclic Redundancy Check Memory Scan 31.1. Features 31.2. Overview 31.2.1. Block Diagram 31.3. Functional Description 31.3.1. Initialization 31.3.2. Operation 31.3.2.1. Checksum 31.3.3. Interrupts 31.3.4. Sleep Mode Operation 31.3.5. Debug Operation 31.4. Register Summary 31.5. Register Description 31.5.1. Control A 31.5.2. Control B 31.5.3. Status 32. CCL - Configurable Custom Logic 32.1. Features 32.2. Overview 32.2.1. Block Diagram 32.2.2. Signal Description 32.2.2.1. CCL Input Selection MUX 32.3. Functional Description 32.3.1. Operation 32.3.1.1. Enable-Protected Configuration 32.3.1.2. Enabling, Disabling, and Resetting 32.3.1.3. Truth Table Logic 32.3.1.4. Truth Table Inputs Selection 32.3.1.5. Filter 32.3.1.6. Edge Detector 32.3.1.7. Sequencer Logic 32.3.1.8. Clock Source Settings 32.3.2. Interrupts 32.3.3. Events 32.3.4. Sleep Mode Operation 32.4. Register Summary 32.5. Register Description 32.5.1. Control A 32.5.2. Sequencer Control 0 32.5.3. Sequencer Control 1 32.5.4. Sequencer Control 2 32.5.5. Interrupt Control 0 32.5.6. Interrupt Control 1 32.5.7. Interrupt Flag 32.5.8. LUT n Control A 32.5.9. LUT n Control B 32.5.10. LUT n Control C 32.5.11. TRUTHn 33. AC - Analog Comparator 33.1. Features 33.2. Overview 33.2.1. Block Diagram 33.2.2. Signal Description 33.3. Functional Description 33.3.1. Initialization 33.3.2. Operation 33.3.2.1. Input Hysteresis 33.3.2.2. Input and Reference Selection 33.3.2.3. Normal Mode 33.3.2.4. Power Modes 33.3.2.5. Window Mode 33.3.3. Events 33.3.4. Interrupts 33.3.5. Sleep Mode Operation 33.4. Register Summary 33.5. Register Description 33.5.1. Control A 33.5.2. Control B 33.5.3. MUX Control 33.5.4. DAC Voltage Reference 33.5.5. Interrupt Control 33.5.6. Status 34. ADC - Analog-to-Digital Converter 34.1. Features 34.2. Overview 34.2.1. Block Diagram 34.2.2. Signal Description 34.3. Functional Description 34.3.1. Definitions 34.3.2. Initialization 34.3.3. Operation 34.3.3.1. Operation Modes 34.3.3.2. Starting a Conversion 34.3.3.3. Clock Generation 34.3.3.4. Conversion Timing 34.3.3.4.1. Single Conversion 34.3.3.4.2. Accumulated Conversion 34.3.3.4.3. Free-Running Conversion 34.3.3.4.4. Adjusting Conversion Time 34.3.3.5. Conversion Result (Output Formats) 34.3.3.6. Accumulation 34.3.3.7. Channel Selection 34.3.3.8. Temperature Measurement 34.3.3.9. Window Comparator 34.3.4. I/O Lines and Connections 34.3.5. Events 34.3.6. Interrupts 34.3.7. Debug Operation 34.3.8. Sleep Mode Operation 34.3.9. Synchronization 34.3.10. Configuration Change Protection 34.4. Register Summary 34.5. Register Description 34.5.1. Control A 34.5.2. Control B 34.5.3. Control C 34.5.4. Control D 34.5.5. Control E 34.5.6. Sample Control 34.5.7. MUX Selection for Positive ADC Input 34.5.8. MUX Selection for Negative ADC Input 34.5.9. Command 34.5.10. Event Control 34.5.11. Interrupt Control 34.5.12. Interrupt Flags 34.5.13. Debug Control 34.5.14. Temporary 34.5.15. Result 34.5.16. Window Comparator Low Threshold 34.5.17. Window Comparator High Threshold 35. DAC - Digital-to-Analog Converter 35.1. Features 35.2. Overview 35.2.1. Block Diagram 35.2.2. Signal Description 35.3. Functional Description 35.3.1. Initialization 35.3.2. Operation 35.3.2.1. Enabling, Disabling and Resetting 35.3.2.2. Starting a Conversion 35.3.2.3. 35.3.2.3.1. Unbuffered Output as Source For Internal Peripherals 35.3.2.3.2. Buffered Output 35.3.3. Sleep Mode Operation 35.4. Register Summary 35.5. Register Description 35.5.1. Control A 35.5.2. DATA 36. PTC - Peripheral Touch Controller 36.1. Features 36.2. Overview 36.3. Block Diagram 36.4. Signal Description 36.5. System Dependencies 36.5.1. I/O Lines 36.5.1.1. Mutual Capacitance Sensor Arrangement 36.5.1.2. Self-Capacitance Sensor Arrangement 36.5.2. Clocks 36.6. Functional Description 37. ZCD - Zero-Cross Detector 37.1. Features 37.2. Overview 37.2.1. Block Diagram 37.2.2. Signal Description 37.3. Functional Description 37.3.1. Initialization 37.3.2. Operation 37.3.2.1. External Resistor Selection 37.3.2.2. ZCD Logic Output 37.3.2.3. Correction for ZCPINV Offset 37.3.2.3.1. Correction By Offset Current 37.3.2.3.2. Correction by AC Coupling 37.3.2.4. Handling VPEAK Variations 37.3.3. Events 37.3.4. Interrupts 37.3.5. Sleep Mode Operation 37.4. Register Summary 37.5. Register Description 37.5.1. Control A 37.5.2. Interrupt Control 37.5.3. Status 38. UPDI - Unified Program and Debug Interface 38.1. Features 38.2. Overview 38.2.1. Block Diagram 38.2.2. Clocks 38.2.3. Physical Layer 38.2.4. Pinout Description 38.3. Functional Description 38.3.1. Principle of Operation 38.3.1.1. UPDI UART 38.3.1.2. BREAK Character 38.3.1.2.1. BREAK in One-Wire Mode 38.3.1.3. SYNCH Character 38.3.1.3.1. SYNCH in One-Wire Mode 38.3.2. Operation 38.3.2.1. UPDI Enabling 38.3.2.1.1. One-Wire Enable 38.3.2.1.1.1. UPDI Enable 38.3.2.2. UPDI Disabling 38.3.2.2.1. Disable During Start-Up 38.3.2.2.1.1. Time-Out Disable 38.3.2.2.1.2. Incorrect SYNCH Pattern 38.3.2.2.2. UPDI Regular Disable 38.3.2.3. UPDI Communication Error Handling 38.3.2.4. Direction Change 38.3.3. UPDI Instruction Set 38.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 38.3.3.2. STS - Store Data to Data Space Using Direct Addressing 38.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 38.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing 38.3.3.5. LDCS - Load Data from Control and Status Register Space 38.3.3.6. STCS - Store Data to Control and Status Register Space 38.3.3.7. REPEAT - Set Instruction Repeat Counter 38.3.3.8. KEY - Set Activation Key or Send System Information Block 38.3.4. CRC Checking of Flash During Boot 38.3.5. Inter-Byte Delay 38.3.6. System Information Block 38.3.7. Enabling of Key Protected Interfaces 38.3.7.1. Chip Erase 38.3.7.2. NVM Programming 38.3.7.3. User Row Programming 38.3.8. Events 38.3.9. Sleep Mode Operation 38.4. Register Summary 38.5. Register Description 38.5.1. Status A 38.5.2. Status B 38.5.3. Control A 38.5.4. Control B 38.5.5. ASI Key Status 38.5.6. ASI Reset Request 38.5.7. ASI Control A 38.5.8. ASI System Control A 38.5.9. ASI System Status 38.5.10. ASI CRC Status 39. Instruction Set Summary 40. Electrical Characteristics 40.1. Disclaimer 40.2. Absolute Maximum Ratings 40.3. Standard Operating Conditions 40.4. Supply Voltage 40.5. Power Consumption 40.6. Peripherals Power Consumption 40.7. I/O Pins 40.8. Memory Programming Specifications 40.9. Thermal Specifications 40.10. CLKCTRL 40.10.1. Internal Oscillators 40.10.2. XOSC32K 40.10.3. External Clock 40.10.4. PLL 40.10.5. System Clock 40.11. RST and BOD 40.12. VREF 40.13. USART 40.14. SPI 40.15. TWI 40.16. DAC 40.17. ADC 40.18. AC 40.19. PTC 40.20. ZCD 40.21. UPDI 41. Characteristics Graphs 41.1. Power Consumption 41.1.1. Active Mode 41.1.2. Idle Sleep Mode 41.1.3. Standby Sleep Mode 41.1.4. Power-Down Sleep Mode 41.1.5. Power Consumption in Reset Mode 41.2. Peripheral Power Consumption 41.2.1. ADC 41.2.2. AC 41.2.3. BOD 41.2.4. DAC 41.2.5. Program Memory 41.2.6. OSC32K 41.2.7. RTC 41.2.8. TCA 41.2.9. TCB 41.2.10. TCD 41.2.11. TWI 41.2.12. USART 41.2.13. VREF 41.2.14. WDT 41.3. CLKCTRL 41.3.1. OSCHF 41.3.2. XOSC32K 41.3.3. Wake-up Time 41.4. Reset Controller 41.4.1. RST 41.4.2. Start-up Timer 41.4.3. POR 41.4.4. BOD 41.5. I/O Pins 41.6. VREF 41.6.1. ADC0REF 41.6.2. ACREF 41.6.3. DACREF 41.7. ADC 41.7.1. ADC - 12-Bit Single Ended Mode 41.7.2. ADC - 12-Bit Differential Mode 41.8. Temperature Sensor 41.9. AC 41.10. DAC 41.10.1. DAC - 10-Bit Mode 41.10.2. DAC - 8-Bit Mode 41.11. ZCD 42. Ordering Information 43. Package Drawings 43.1. Online Package Drawings 43.2. Package Marking Information 43.2.1. 28-Pin SPDIP 43.2.2. 28-Pin SOIC 43.2.3. 28-Pin SSOP 43.2.4. 32-Pin VQFN 43.2.5. 32-Pin TQFP 43.2.6. 48-Pin VQFN 43.2.7. 48-Pin TQFP 43.3. 28-Pin SPDIP 43.4. 28-Pin SOIC 43.5. 28-Pin SSOP 43.6. 32-Pin VQFN 43.7. 32-Pin VQFN Wettable Flanks 43.8. 32-Pin TQFP 43.9. 48-Pin VQFN 43.10. 48-Pin VQFN Wettable Flanks 43.11. 48-Pin TQFP 44. Data Sheet Revision History 44.1. Rev. B - 06/2021 44.2. Rev. A - 06/2020 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service