8-bit AVR Microcontroller

Overview

The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128kHz, as the next figure. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted. The Watchdog Reset (WDR) instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the device resets and executes from the Reset Vector.

Figure 1. Watchdog Timer

The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON. See Procedure for Changing the Watchdog Timer Configuration for details.

Table 1. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON Safety Level WDT Initial State How to Disable the WDT How to Change Time-out
Unprogrammed 1 Disabled Protected change sequence No limitations
Programmed 2 Enabled Always enabled Protected change sequence