Contents

Introduction Feature 3. Description 4. Configuration Summary 5. Ordering Information 6. Block Diagram 7. Pin Configurations 7.1. Pin Descriptions 7.1.1. VCC 7.1.2. GND 7.1.3. Port A (PA[7:0]) 7.1.4. Port B (PB[3:0]) 7.1.5. RESET 8. I/O Multiplexing 9. General Information 9.1. Resources 9.2. Data Retention 9.3. About Code Examples 10. AVR CPU Core 10.1. Overview 10.2. Features 10.3. Block Diagram 10.4. ALU – Arithmetic Logic Unit 10.5. Status Register 10.6. General Purpose Register File 10.7. The X-register, Y-register, and Z-register 10.8. Stack Pointer 10.9. Accessing 16-bit Registers 10.10. Instruction Execution Timing 10.11. Reset and Interrupt Handling 10.11.1. Interrupt Response Time 10.12. Register Description 10.12.1. Configuration Change Protection Register 10.12.2. Stack Pointer Register Low and High byte 10.12.3. Status Register 11. AVR Memories 11.1. Overview 11.2. Features 11.3. In-System Reprogrammable Flash Program Memory 11.4. SRAM Data Memory 11.4.1. Data Memory Access Times 11.5. I/O Memory 12. Clock System 12.1. Overview 12.2. Clock Distribution 12.3. Clock Subsystems 12.3.1. CPU Clock – clkCPU 12.3.2. I/O Clock – clkI/O 12.3.3. NVM Clock – clkNVM 12.3.4. ADC Clock – clkADC 12.4. Clock Sources 12.4.1. Calibrated Internal 8MHz Oscillator 12.4.2. External Clock 12.4.3. Internal 128kHz Oscillator 12.4.4. Switching Clock Source 12.4.5. Default Clock Source 12.5. System Clock Prescaler 12.5.1. Switching Prescaler Setting 12.6. Starting 12.6.1. Starting from Reset 12.6.2. Starting from Power-Down Mode 12.6.3. Starting from Idle / ADC Noise Reduction / Standby Mode 12.7. Register Description 12.7.1. Clock Main Settings Register 12.7.2. Oscillator Calibration Register 12.7.3. Clock Prescaler Register 13. Power Management and Sleep Modes 13.1. Overview 13.2. Features 13.3. Sleep Modes 13.3.1. Idle Mode 13.3.2. ADC Noise Reduction Mode 13.3.3. Power-Down Mode 13.3.4. Standby Mode 13.4. Power Reduction Register 13.5. Minimizing Power Consumption 13.5.1. Analog Comparator 13.5.2. Analog to Digital Converter 13.5.3. Internal Voltage Reference 13.5.4. Watchdog Timer 13.5.5. Port Pins 13.6. Register Description 13.6.1. Sleep Mode Control Register 13.6.2. Power Reduction Register 14. SCRST - System Control and Reset 14.1. Overview 14.2. Features 14.3. Resetting the AVR 14.4. Reset Sources 14.4.1. Power-on Reset 14.4.2. VCC Level Monitoring 14.4.3. External Reset 14.4.4. Watchdog System Reset 14.5. Watchdog Timer 14.5.1. Overview 14.5.2. Procedure for Changing the Watchdog Timer Configuration 14.5.2.1. Safety Level 1 14.5.2.2. Safety Level 2 14.5.3. Code Examples 14.6. Register Description 14.6.1. Watchdog Timer Control Register 14.6.2. VCC Level Monitoring Control and Status register 14.6.3. Reset Flag Register 15. Interrupts 15.1. Overview 15.2. Interrupt Vectors 15.3. External Interrupts 15.3.1. Low Level Interrupt 15.3.2. Pin Change Interrupt Timing 15.4. Register Description 15.4.1. External Interrupt Control Register A 15.4.2. External Interrupt Mask Register 15.4.3. External Interrupt Flag Register 15.4.4. Pin Change Interrupt Control Register 15.4.5. Pin Change Interrupt Flag Register 15.4.6. Pin Change Mask Register 0 15.4.7. Pin Change Mask Register 1 16. I/O-Ports 16.1. Overview 16.2. Features 16.3. I/O Pin Equivalent Schematic 16.4. Ports as General Digital I/O 16.4.1. Configuring the Pin 16.4.2. Toggling the Pin 16.4.3. Break-Before-Make Switching 16.4.4. Reading the Pin Value 16.4.5. Digital Input Enable and Sleep Modes 16.4.6. Unconnected Pins 16.4.7. Program Example 16.4.8. Alternate Port Functions 16.4.8.1. Alternate Functions of Port A 16.4.8.2. Alternate Functions of Port B 16.5. Register Description 16.5.1. Port A Input Pins Address 16.5.2. Port A Data Direction Register 16.5.3. Port A Data Register 16.5.4. Port A Pull-up Enable Control Register 16.5.5. Port B Input Pins Address 16.5.6. Port B Data Direction Register 16.5.7. Port B Data Register 16.5.8. Port B Pull-up Enable Control Register 16.5.9. Port Control Register 17. USART - Universal Synchronous Asynchronous Receiver Transceiver 17.1. Overview 17.2. Features 17.3. Block Diagram 17.4. Clock Generation 17.4.1. Internal Clock Generation – The Baud Rate Generator 17.4.2. Double Speed Operation (U2X0) 17.4.3. External Clock 17.4.4. Synchronous Clock Operation 17.5. Frame Formats 17.5.1. Parity Bit Calculation 17.6. USART Initialization 17.7. Data Transmission – The USART Transmitter 17.7.1. Sending Frames with 5 to 8 Data Bits 17.7.2. Sending Frames with 9 Data Bit 17.7.3. Transmitter Flags and Interrupts 17.7.4. Parity Generator 17.7.5. Disabling the Transmitter 17.8. Data Reception – The USART Receiver 17.8.1. Receiving Frames with 5 to 8 Data Bits 17.8.2. Receiving Frames with 9 Data Bits 17.8.3. Receive Compete Flag and Interrupt 17.8.4. Receiver Error Flags 17.8.5. Parity Checker 17.8.6. Disabling the Receiver 17.8.7. Flushing the Receive Buffer 17.9. Asynchronous Data Reception 17.9.1. Asynchronous Clock Recovery 17.9.2. Asynchronous Data Recovery 17.9.3. Asynchronous Operational Range 17.9.4. Start Frame Detection 17.10. Multi-Processor Communication Mode 17.10.1. Using MPCMn 17.11. Examples of Baud Rate Setting 17.12. Register Description 17.12.1. USART I/O Data Register 0 17.12.2. USART Control and Status Register 0 A 17.12.3. USART Control and Status Register 0 B 17.12.4. USART Control and Status Register 0 C 17.12.5. USART Control and Status Register 0 D 17.12.6. USART Baud Rate 0 Register Low and High byte 18. USARTSPI - USART in SPI Mode 18.1. Overview 18.2. Features 18.3. Clock Generation 18.4. SPI Data Modes and Timing 18.5. Frame Formats 18.5.1. USART MSPIM Initialization 18.6. Data Transfer 18.6.1. Transmitter and Receiver Flags and Interrupts 18.6.2. Disabling the Transmitter or Receiver 18.7. AVR USART MSPIM vs. AVR SPI 18.8. Register Description 19. TC0 - 16-bit Timer/Counter0 with PWM 19.1. Overview 19.2. Features 19.3. Block Diagram 19.4. Definitions 19.5. Registers 19.6. Accessing 16-bit Timer/Counter Registers 19.6.1. Reusing the Temporary High Byte Register 19.7. Timer/Counter Clock Sources 19.7.1. Internal Clock Source - Prescaler 19.7.2. Prescaler Reset 19.7.3. External Clock Source 19.8. Counter Unit 19.9. Input Capture Unit 19.9.1. Input Capture Trigger Source 19.9.2. Noise Canceler 19.9.3. Using the Input Capture Unit 19.10. Output Compare Units 19.10.1. Force Output Compare 19.10.2. Compare Match Blocking by TCNT0 Write 19.10.3. Using the Output Compare Unit 19.11. Compare Match Output Unit 19.11.1. Compare Output Mode and Waveform Generation 19.12. Modes of Operation 19.12.1. Normal Mode 19.12.2. Clear Timer on Compare Match (CTC) Mode 19.12.3. Fast PWM Mode 19.12.4. Phase Correct PWM Mode 19.12.5. Phase and Frequency Correct PWM Mode 19.13. Timer/Counter Timing Diagrams 19.14. Register Description 19.14.1. Timer/Counter0 Control Register A 19.14.2. Timer/Counter0 Control Register B 19.14.3. Timer/Counter0 Control Register C 19.14.4. Timer/Counter 0 Low and High byte 19.14.5. Output Comparte Register A 0 Low and High byte 19.14.6. Output Comparte Register B 0 Low and High byte 19.14.7. Input Capture Register 0 Low and High byte 19.14.8. Timer/Counter0 Interrupt Mask Register 19.14.9. Timer/Counter0 Interrupt Flag Register 19.14.10. General Timer/Counter Control Register 20. AC - Analog Comparator 20.1. Overview 20.2. Features 20.3. Block Diagram 20.4. Register Description 20.4.1. Analog Comparator Control and Status Register 20.4.2. Analog Comparator Control and Status Register 0 20.4.3. Digital Input Disable Register 0 21. ADC - Analog to Digital Converter 21.1. Overview 21.2. Features 21.3. Block Diagram 21.4. Operation 21.5. Starting a Conversion 21.6. Prescaling and Conversion Timing 21.7. Changing Channel or Reference Selection 21.8. ADC Input Channels 21.9. ADC Voltage Reference 21.10. ADC Noise Canceler 21.11. Analog Input Circuitry 21.12. Analog Noise Canceling Techniques 21.13. ADC Accuracy Definitions 21.14. ADC Conversion Result 21.14.1. Single-Ended Conversion 21.15. Register Description 21.15.1. ADC Multiplexer Selection Register 21.15.2. ADC Control and Status Register A 21.15.3. ADC Control and Status Register B 21.15.4. ADC Data Register Low and High Byte (ADLAR=0) 21.15.5. ADC Data Register Low and High Byte (ADLAR=1) 21.15.6. Digital Input Disable Register 0 22. MEMPROG- Memory Programming 22.1. Overview 22.2. Features 22.3. Non-Volatile Memories (NVM) 22.3.1. Non-Volatile Memory Lock Bits 22.3.2. Flash Memory 22.3.3. Configuration Section 22.3.3.1. Latching of Configuration Bits 22.3.4. Signature Section 22.3.4.1. Signature Row Summary 22.3.4.1.1. Device ID n 22.3.4.1.2. Serial Number Byte n 22.3.5. Calibration Section 22.4. Accessing the NVM 22.4.1. Addressing the Flash 22.4.2. Reading the Flash 22.4.3. Programming the Flash 22.4.3.1. Chip Erase 22.4.3.2. Erasing the Code Section 22.4.3.3. Writing a Code Word 22.4.3.4. Erasing the Configuration Section 22.4.3.5. Writing a Configuration Word 22.4.4. Reading NVM Lock Bits 22.4.5. Writing NVM Lock Bits 22.5. Self programming 22.6. External Programming 22.6.1. Entering External Programming Mode 22.6.2. Exiting External Programming Mode 22.7. Register Description 22.7.1. Non-Volatile Memory Control and Status Register 22.7.2. Non-Volatile Memory Command Register 23. TPI-Tiny Programming Interface 23.1. Overview 23.2. Features 23.3. Block Diagram 23.4. Physical Layer of Tiny Programming Interface 23.4.1. Enabling 23.4.2. Disabling 23.4.3. Frame Format 23.4.4. Parity Bit Calculation 23.4.5. Supported Characters 23.4.6. Operation 23.4.7. Serial Data Reception 23.4.8. Serial Data Transmission 23.4.9. Collision Detection Exception 23.4.10. Direction Change 23.4.11. Access Layer of Tiny Programming Interface 23.4.11.1. Message format 23.4.11.2. Exception Handling and Synchronisation 23.5. Instruction Set 23.5.1. SLD - Serial LoaD from data space using indirect addressing 23.5.2. SST - Serial STore to data space using indirect addressing 23.5.3. SSTPR - Serial STore to Pointer Register 23.5.4. SIN - Serial IN from i/o space using direct addressing 23.5.5. SOUT - Serial OUT to i/o space using direct addressing 23.5.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing 23.5.7. SSTCS - Serial STore data to Control and Status space using direct addressing 23.5.8. SKEY - Serial KEY signaling 23.6. Accessing the Non-Volatile Memory Controller 23.7. Control and Status Space Register Descriptions 23.7.1. Tiny Programming Interface Identification Register 23.7.2. Tiny Programming Interface Physical Layer Control Register 23.7.3. Tiny Programming Interface Status Register 24. Electrical Characteristics 24.1. Absolute Maximum Ratings* 24.2. DC Characteristics 24.3. Speed 24.4. Clock Characteristics 24.4.1. Accuracy of Calibrated Internal Oscillator 24.4.2. External Clock Drive 24.5. System and Reset Characteristics 24.5.1. Power-On Reset 24.5.2. VCC Level Monitor 24.6. Analog Comparator Characteristics 24.7. ADC Characteristics 24.8. Serial Programming Characteristics 25. Typical Characteristics 25.1. Active Supply Current 25.2. Idle Supply Current 25.3. Supply Current of I/O Modules 25.4. Power-down Supply Current 25.5. Pin Driver Strength 25.6. Pin Threshold and Hysteresis 25.7. Analog Comparator Offset 25.8. Pin Pull-up 25.9. Internal Oscillator Speed 25.10. VLM Thresholds 25.11. Current Consumption of Peripheral Units 25.12. Current Consumption in Reset and Reset Pulsewidth 26. Register Summary 26.1. Note 27. Instruction Set Summary 28. Packaging Information 28.1. 8-pin UDFN 28.2. 8-pin SOIC150 28.3. 14-pin SOIC150 29. Errata 29.1. ATtiny102 29.1.1. Rev.A 29.2. ATtiny104 29.2.1. Rev.A 30. Datasheet Revision History 30.1. Rev D - 10/2016 30.2. Rev C - 07/2016 30.3. Rev B - 06/2016 30.4. Rev A - 02/2016 31. Legal Disclaimer