USBHS_DEVEPTIFRx (ISOENPT)

Device Endpoint Interrupt Set Register (Isochronous Endpoints)

This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.

  0x0190 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Device Endpoint Interrupt Set Register (Isochronous Endpoints)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
        NBUSYBKS          
Access                   
Reset        0          
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETS CRCERRIS OVERFIS HBISOFLUSHIS HBISOINERRIS UNDERFIS RXOUTIS TXINIS  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINIS: Transmitted IN Data Interrupt Set

Transmitted IN Data Interrupt Set

Bit 1 – RXOUTIS: Received OUT Data Interrupt Set

Received OUT Data Interrupt Set

Bit 2 – UNDERFIS: Underflow Interrupt Set

Underflow Interrupt Set

Bit 3 – HBISOINERRIS: High Bandwidth Isochronous IN Underflow Error Interrupt Set

High Bandwidth Isochronous IN Underflow Error Interrupt Set

Bit 4 – HBISOFLUSHIS: High Bandwidth Isochronous IN Flush Interrupt Set

High Bandwidth Isochronous IN Flush Interrupt Set

Bit 5 – OVERFIS: Overflow Interrupt Set

Overflow Interrupt Set

Bit 6 – CRCERRIS: CRC Error Interrupt Set

CRC Error Interrupt Set

Bit 7 – SHORTPACKETS: Short Packet Interrupt Set

Short Packet Interrupt Set

Bit 12 – NBUSYBKS: Number of Busy Banks Interrupt Set

Number of Busy Banks Interrupt Set