Device Endpoint Interrupt Clear Register (Isochronous Endpoints)
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTISRx.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SHORTPACKETC | CRCERRIC | OVERFIC | HBISOFLUSHIC | HBISOINERRIC | UNDERFIC | RXOUTIC | TXINIC | ||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Transmitted IN Data Interrupt Clear
Received OUT Data Interrupt Clear
Underflow Interrupt Clear
High Bandwidth Isochronous IN Underflow Error Interrupt Clear
High Bandwidth Isochronous IN Flush Interrupt Clear
Overflow Interrupt Clear
CRC Error Interrupt Clear
Short Packet Interrupt Clear