Embedded Characteristics
- Debug access to all memory and registers in the system, including Cortex-M register bank, when the core is running, halted, or held in reset.
- Serial Wire Debug Port (SW-DP) debug access (ADIv5.1 with no
multidrop mode support).
- Flash Patch and Breakpoint (FPB) unit for implementing
breakpoints and code patches.
- Data Watchpoint and Trace (DWT) unit for implementing
watchpoints, data tracing, and system profiling.
- Instrumentation Trace Macrocell (ITM) for support of printf
style debugging.
- 6-pin Embedded Trace Macrocell (ETM) for instruction trace
stream, including CoreSightâ„¢ Trace Port Interface Unit (TPIU).
- IEEE1149.1 JTAG Boundary scan on All Digital Pins.