The MediaLB system clock is generated by a single MediaLB Controller. The MediaLB Controller outputs the clock on the MLBCLK pin, which is connected to the clock input of all other MediaLB Devices in the system. All MediaLB Devices (including the MediaLB Controller), share the signals connected to the MLBSIG and MLBDAT pins.
Once per physical channel (quadlet) on the MLBSIG line, the Controller outputs the ChannelAddress, the transmitting Device outputs Command, and the receiving Device outputs RxStatus. Therefore, each Device must set MLBSIG high impedance when not driving in order to allow the other Devices to drive it. Once per physical channel, the transmitting Device must also drive data onto the MLBDAT line, and set the line to high impedance for physical channels not allocated to that particular Device. As illustrated in the following figure, pull-down resistors are required on each signal to keep them in a known state when neither the Controller nor a Device is driving. Resistors are also recommended near the Controller and Device transmit lines for series termination and rise/fall time control. The clock line (MLBCLK) may optionally have AC-parallel termination near the farthest Device from the Controller to ensure a clean clock by minimizing reflections.
