USBHS_DEVEPTISRx

Device Endpoint Interrupt Status Register (Control, Bulk, Interrupt Endpoints)

This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.

  0x0130 + x*0x04 [x=0..9] 32 Read/Write 0   10 x

Device Endpoint Interrupt Status Register (Control, Bulk, Interrupt Endpoints)

Bit  31 30 29 28 27 26 25 24  
    BYCT[10:4]  
Access                   
Reset    0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  BYCT[3:0]   CFGOK CTRLDIR RWALL  
Access                   
Reset  0 0 0 0   0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CURRBK[1:0] NBUSYBK[1:0]     DTSEQ[1:0]  
Access                   
Reset  0 0 0 0     0 0  
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKET STALLEDI OVERFI NAKINI NAKOUTI RXSTPI RXOUTI TXINI  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINI: Transmitted IN Data Interrupt

Transmitted IN Data Interrupt

For control endpoints:

0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet.

1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1.

For bulk and interrupt IN endpoints:

0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no effect on the endpoint FIFO. USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.

1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if TXINE = 1.

The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.

This bit is inactive (cleared) for bulk and interrupt OUT endpoints.

Bit 1 – RXOUTI: Received OUT Data Interrupt

Received OUT Data Interrupt

For control endpoints:

0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt and frees the bank.

1: Set when the current bank contains a bulk OUT packet (data or status stage). This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.

For bulk and interrupt OUT endpoints:

0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt, which has no effect on the endpoint FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.

1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.

The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.

This bit is inactive (cleared) for bulk and interrupt IN endpoints.

Bit 2 – RXSTPI: Received SETUP Interrupt

Received SETUP Interrupt

This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers a PEP_x interrupt if RXSTPE = 1.

It is cleared by writing a one to the RXSTPIC bit. This acknowledges the interrupt and frees the bank.

This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints.

Bit 3 – NAKOUTI: NAKed OUT Interrupt

NAKed OUT Interrupt

ValueDescription
0

Cleared when NAKOUTIC = 1. This acknowledges the interrupt.

1

Set when a NAK handshake has been sent in response to an OUT request from the host. This triggers a PEP_x interrupt if NAKOUTE = 1.

Bit 4 – NAKINI: NAKed IN Interrupt

NAKed IN Interrupt

ValueDescription
0

Cleared when NAKINIC = 1. This acknowledges the interrupt.

1

Set when a NAK handshake has been sent in response to an IN request from the host. This triggers a PEP_x interrupt if NAKINE = 1.

Bit 5 – OVERFI: Overflow Interrupt

Overflow Interrupt

For all endpoint types, an overflow can occur during the OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.

ValueDescription
0

Cleared when the OVERFIC bit is written to one. This acknowledges the interrupt.

1

Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1.

Bit 6 – STALLEDI: STALLed Interrupt

STALLed Interrupt

ValueDescription
0

Cleared when STALLEDIC = 1. This acknowledges the interrupt.

1

Set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a one to the STALLRQS bit). This triggers a PEP_x interrupt if STALLEDE = 1.

Bit 7 – SHORTPACKET: Short Packet Interrupt

Short Packet Interrupt

ValueDescription
0

Cleared when SHORTPACKETC = 1. This acknowledges the interrupt.

1

Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.SHORTPACKETE = 1.

Bits 9:8 – DTSEQ[1:0]: Data Toggle Sequence

Data Toggle Sequence

This field is set to indicate the PID of the current bank:

For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not relative to the current bank.

For OUT transfers, this value indicates the last data toggle sequence received on the current bank.

By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0.

ValueNameDescription
0 DATA0

Data0 toggle sequence

1 DATA1

Data1 toggle sequence

2 DATA2

Reserved for high-bandwidth isochronous endpoint

3 MDATA

Reserved for high-bandwidth isochronous endpoint

Bits 13:12 – NBUSYBK[1:0]: Number of Busy Banks

Number of Busy Banks

This field is set to indicate the number of busy banks:

For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers a PEP_x interrupt if NBUSYBKE = 1.

For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers a PEP_x interrupt if NBUSYBKE = 1.

When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank.

A PEP_x interrupt is triggered if:

ValueNameDescription
0 0_BUSY

0 busy bank (all banks free)

1 1_BUSY

1 busy bank

2 2_BUSY

2 busy banks

3 3_BUSY

3 busy banks

• for IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free;

• for OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy.

Bits 15:14 – CURRBK[1:0]: Current Bank

Current Bank

This bit is set for non-control endpoints, to indicate the current bank:

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

ValueNameDescription
0 BANK0

Current bank is bank0

1 BANK1

Current bank is bank1

2 BANK2

Current bank is bank2

3

Reserved

Bit 16 – RWALL: Read/Write Allowed

Read/Write Allowed

This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.

This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.

This bit is never set if USBHS_DEVEPTIMRx.STALLRQ = 1 or in case of error.

This bit is cleared otherwise.

This bit should not be used for control endpoints.

Bit 17 – CTRLDIR: Control Direction

Control Direction

ValueDescription
0

Cleared after a SETUP packet to indicate that the following packet is an OUT packet.

1

Set after a SETUP packet to indicate that the following packet is an IN packet.

Bit 18 – CFGOK: Configuration OK Status

Configuration OK Status

This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1.

This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size (USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this endpoint and to the maximal FIFO size (i.e., the DPRAM size).

If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and USBHS_DEVEPTCFGx.EPSIZE fields.

Bits 30:20 – BYCT[10:0]: Byte Count

Byte Count

This field is set with the byte count of the FIFO.

For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host.

For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte read by the software from the endpoint.

This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.