PWM_CCNTx

PWM Channel Counter Register

Only the first 16 bits (channel counter size) are significant.

  0x0214 + x*0x20 [x=0..3] 32 Read-only 0x00000000   4 32 -1

PWM Channel Counter Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  CNT[23:16]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CNT[15:8]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CNT[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bits 23:0 – CNT[23:0]: Channel Counter Register

Channel Counter Register

Channel counter value. This register is reset when:

• the channel is enabled (writing CHIDx in the PWM_ENA register).

• the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left-aligned.