GMAC_EFRSH

GMAC PTP Event Frame Received Seconds High Register

  0x0EC 32 Read-only 0x00000000  

GMAC PTP Event Frame Received Seconds High Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  RUD[15:8]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  RUD[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bits 15:0 – RUD[15:0]: Register Update

Register Update

The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.