USBHS_DEVEPTIDRx

Device Endpoint Interrupt Disable Register (Control, Bulk, Interrupt Endpoints)

This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

  0x0220 + x*0x04 [x=0..9] 32 Read/Write 0   10 4 x
Parent topic: Register Summary

Device Endpoint Interrupt Disable Register (Control, Bulk, Interrupt Endpoints)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
          STALLRQC   NYETDISC EPDISHDMAC  
Access                   
Reset          0   0 0  
Bit  15 14 13 12 11 10 9 8  
    FIFOCONC   NBUSYBKEC          
Access                   
Reset    0   0          
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETEC STALLEDEC OVERFEC NAKINEC NAKOUTEC RXSTPEC RXOUTEC TXINEC  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bit 0 – TXINEC: Transmitted IN Interrupt Clear

Transmitted IN Interrupt Clear

Bit 1 – RXOUTEC: Received OUT Data Interrupt Clear

Received OUT Data Interrupt Clear

Bit 2 – RXSTPEC: Received SETUP Interrupt Clear

Received SETUP Interrupt Clear

Bit 3 – NAKOUTEC: NAKed OUT Interrupt Clear

NAKed OUT Interrupt Clear

Bit 4 – NAKINEC: NAKed IN Interrupt Clear

NAKed IN Interrupt Clear

Bit 5 – OVERFEC: Overflow Interrupt Clear

Overflow Interrupt Clear

Bit 6 – STALLEDEC: STALLed Interrupt Clear

STALLed Interrupt Clear

Bit 7 – SHORTPACKETEC: Shortpacket Interrupt Clear

Shortpacket Interrupt Clear

Bit 12 – NBUSYBKEC: Number of Busy Banks Interrupt Clear

Number of Busy Banks Interrupt Clear

Bit 14 – FIFOCONC: FIFO Control Clear

FIFO Control Clear

Bit 16 – EPDISHDMAC: Endpoint Interrupts Disable HDMA Request Clear

Endpoint Interrupts Disable HDMA Request Clear

Bit 17 – NYETDISC: NYET Token Disable Clear

NYET Token Disable Clear

Bit 19 – STALLRQC: STALL Request Clear

STALL Request Clear