SPI Status Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SPIENS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SFERR | UNDES | TXEMPTY | NSSR | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRES | MODF | TDRE | RDRF | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Receive Data Register Full (cleared by reading SPI_RDR)
0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the internal shift register to SPI_RDR since the last read of SPI_RDR.
Transmit Data Register Empty (cleared by writing SPI_TDR)
0: Data has been written to SPI_TDR and not yet transferred to the internal shift register.
1: The last data written in SPI_TDR has been transferred to the internal shift register.
TDRE is cleared when the SPI is disabled or at reset. Enabling the SPI sets the TDRE flag.
Mode Fault Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No mode fault has been detected since the last read of SPI_SR. |
| 1 | A mode fault occurred since the last read of SPI_SR. |
Overrun Error Status (cleared on read)
An overrun occurs when SPI_RDR is loaded at least twice from the internal shift register since the last read of SPI_RDR.
| Value | Description |
|---|---|
| 0 | No overrun has been detected since the last read of SPI_SR. |
| 1 | An overrun has occurred since the last read of SPI_SR. |
NSS Rising (cleared on read)
| Value | Description |
|---|---|
| 0 | No rising edge detected on NSS pin since the last read of SPI_SR. |
| 1 | A rising edge occurred on NSS pin since the last read of SPI_SR. |
Transmission Registers Empty (cleared by writing SPI_TDR)
| Value | Description |
|---|---|
| 0 | As soon as data is written in SPI_TDR. |
| 1 | SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay. |
Underrun Error Status (Slave mode only) (cleared on read)
| Value | Description |
|---|---|
| 0 | No underrun has been detected since the last read of SPI_SR. |
| 1 | A transfer starts whereas no data has been loaded in SPI_TDR. |
Slave Frame Error (cleared on read)
| Value | Description |
|---|---|
| 0 | There is no frame error detected for a slave access since the last read of SPI_SR. |
| 1 | In Slave mode, the Chip Select raised while the character defined in SPI_CSR0.BITS was not complete. |
SPI Enable Status
| Value | Description |
|---|---|
| 0 | SPI is disabled. |
| 1 | SPI is enabled. |