High-speed mode is enabled when a one is written to TWIHS_CR.HSEN. Furthermore, the analog pad filter must be enabled, a one must be written to TWIHS_FILTR.PADFEN and the FILT bit must be cleared. TWIHS High-speed mode operation is similar to TWIHS operation with the following exceptions:
- 1.A master code is received first at normal speed before entering High-speed mode period.
- 2.When TWIHS High-speed mode is active, clock stretching is only allowed after acknowledge (ACK), not-acknowledge (NACK), START (S) or REPEATED START (Sr) (as consequence OVF may happen).
TWIHS High-speed mode allows transfers of up to 3.4 Mbit/s.
The TWIHS slave in High-speed mode requires that slave clock stretching is disabled (SCLWSDIS bit at ‘1’). The peripheral clock must run at a minimum of 11 MHz (assuming the system has no latency).
Note: When slave clock stretching is disabled, the TWIHS_RHR must always be read before
receiving the next data (MASTER write frame). It is strongly recommended to use either the
polling method on the RXRDY flag in TWIHS_SR, or the DMA. If the receive is managed by an
interrupt, the TWIHS interrupt priority must be set to the right level and its latency
minimized to avoid receive overrun.
Note: When slave clock stretching is disabled, the TWIHS_THR must be filled with the first
data to send before the beginning of the frame (MASTER read frame). It is strongly
recommended to use either the polling method on the TXRDY flag in TWIHS_SR, or the DMA. If the transmit
is managed by an interrupt, the TWIHS interrupt priority must be set to the right level and
its latency minimized to avoid transmit underrun.