Clock Stretching in Write Mode

The clock is tied low if the internal shifter and TWIHS_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWIHS_RHR is read.

The figure below describes the clock stretching in Write mode.

Figure 1. Clock Stretching in Write Mode

Notes:

1. 1.At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.
2. 2.SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the mechanism is finished.