HBI Channel Error 1 Register
HCERn status bits are set when hardware detects hardware errors on the given logical channel, including:
• Channel opened, but not enabled,
• Channel programmed with invalid channel type, or
• Out-of-range PML for asynchronous or control Tx channels
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
CERR: Bitwise Channel Error Bit [63[31:24] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CERR: Bitwise Channel Error Bit [63[23:16] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CERR: Bitwise Channel Error Bit [63[15:8] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CERR: Bitwise Channel Error Bit [63[7:0] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
32]
CERR[n] = 1 indicates that a fatal error occurred on channel n.