I2SC_IMR

I2SC Interrupt Mask Register

  0x1C 32 Read-only 0x00000000  
Parent topic: Register Summary

I2SC Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
    TXUR TXRDY     RXOR RXRDY    
Access    R R     R R    
Reset    0 0     0 0    

Bit 1 – RXRDY: Receiver Ready Interrupt Disable

Receiver Ready Interrupt Disable

ValueDescription
0

The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to ’1’.
1

The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to ’1’.

Bit 2 – RXOR: Receiver Overrun Interrupt Disable

Receiver Overrun Interrupt Disable

ValueDescription
0

The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to ’1’.
1

The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to ’1’.

Bit 5 – TXRDY: Transmit Ready Interrupt Disable

Transmit Ready Interrupt Disable

ValueDescription
0

The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to ’1’.
1

The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to ’1’.

Bit 6 – TXUR: Transmit Underflow Interrupt Disable

Transmit Underflow Interrupt Disable

ValueDescription
0

The corresponding interrupt is disabled. This bit is cleared when the corresponding bit in I2SC_IDR is written to ’1’.
1

The corresponding interrupt is enabled. This bit is set when the corresponding bit in I2SC_IER is written to ’1’.