Register Write Protection

To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR).

If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading the PMC_WPSR.

The following registers are write-protected when the WPEN bit is set in PMC_WPMR:

• PMC System Clock Disable Register
• PMC Peripheral Clock Enable Register 0
• PMC Peripheral Clock Disable Register 0
• PMC Clock Generator Main Oscillator Register
• PMC Clock Generator Main Clock Frequency Register
• PMC Clock Generator PLLA Register
• PMC UTMI Clock Configuration Register
• PMC Master Clock Register
• PMC USB Clock Register
• PMC Programmable Clock Register
• PMC Fast Startup Mode Register
• PMC Fast Startup Polarity Register
• PMC Peripheral Clock Enable Register1
• PMC Pheripheral Clock Disable Register1
• PMC Oscillator Calibration Register
• PMC SleepWalking Enable Register 0
• PMC SleepWalking Disable Register 0
• PLL Maximum Multiplier Value Register
• PMC SleepWalking Enable Register 1
• PMC SleepWalking Disable Register 1