USBHS_DEVICR

Device Global Interrupt Clear Register

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_DEVISR.

  0x0008 32 Write-only    
Parent topic: Register Summary

Device Global Interrupt Clear Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
    UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC  
Access                   
Reset                   

Bit 0 – SUSPC: Suspend Interrupt Clear

Suspend Interrupt Clear

Bit 1 – MSOFC: Micro Start of Frame Interrupt Clear

Micro Start of Frame Interrupt Clear

Bit 2 – SOFC: Start of Frame Interrupt Clear

Start of Frame Interrupt Clear

Bit 3 – EORSTC: End of Reset Interrupt Clear

End of Reset Interrupt Clear

Bit 4 – WAKEUPC: Wakeup Interrupt Clear

Wakeup Interrupt Clear

Bit 5 – EORSMC: End of Resume Interrupt Clear

End of Resume Interrupt Clear

Bit 6 – UPRSMC: Upstream Resume Interrupt Clear

Upstream Resume Interrupt Clear