Revision History

Table 1. Rev. E - 12/2020
Section Name or Type	Update Description
Features	Updated 256 MB to 128 MB for the Memories section.
Configuration Summary	Removed USB type for LQFP Packages
Pinout	Corrected values in the Signal column for the 64-Lead Package Pinout
Power Considerations	Updated Power Supplies Added a Note to the end of the Backup Mode section
Product Mapping	Removed an erroneous figure reference.
Debug and Test Features	Added information regarding multidrop support to the second item in Embedded Characteristics
SAM-BA Boot Program	Updated the formatting of Embedded Characteristics to read properly Updated the temperature verbiage in Hardware and Software Constraints
FFPI	Updated Device Configuration with new information for the Oscillator in Bypass mode Updated Flash Write Command with additional text for the WP Command
EFC	Updated Embedded Flash Organization with new information for the Flash Address Space Updated the following Sections with new information for Flash error: Write Commands Erase Commands Lock Bit Protection GPNVM Bit User Signature Area
SUPC	Added a note to the Supply Monitor section
RSTC	Updated General Reset with a new signal for NRST on the General Reset Timing Diagram
PMC	Updated Main Crystal Oscillator in the Clock Generator section with new SLCK periods Updated the Register Summary to properly display Updated the bit numbering in the PMC_PCER1 and PMC_PCSR1 Registers
SDRAMC	Updated the table for the CASbit for the SDRAMC_CR Register
SMC	Updated the Register Offsets and Offset Equations for Proper display for the following registers: SMC_CYCLE SMC_PULSE SMC_MODE SMC_SETUP
XDMAC	Updated DMA Controller Peripheral Connections with new information in the table for channel 1, transmit 31
GMAC	Updated MAC Transmit Blockwith the removal of erroneous text Updated the register properties for the following registers: OTLO OTHI FT BCFT MFT ORLO ORHI FR BCFR MFR
USBHS	Updated the SPEED bit description in the USBHS_SR Register
HSMCI	Updated the following registers: HSMCI_RSPR: Added a new note HSMCI_FIFOx: New register offset
QSPI	Updated the Description with new text for Master Mode Updated the WDRBT Bit description in the QSPI_MR Register
TWIHS	Added a description to the LOCKCLR bit in the TWIHS_CR register
MCAN	Updated the reset property for the MCAN_CREL Register
AFEC	Added a new table to the TRANSFER bit of the AFEC_MR register
Electrical Characteristics for SAM V70/V71	Updated the VDDIO Supply Monitor Table with a new note Updated the table in 32.768 kHz Crystal Oscillator Characteristics Updated the Max Spec in the table for XIN32 Clock Characteristics in Bypass Mode
Electrical Characteristics for SAM E70/S70	Updated the VDDIO Supply Monitor Table with a new note Updated the table in 32.768 kHz Crystal Oscillator Characteristics Updated the Max Spec in the table for XIN32 Clock Characteristics in Bypass Mode

Table 2. Rev. D - 02/2019
Section Name or Type	Update Description
Signal Description	Updated the Signal Description List.
Input/Output Lines	Updated text in ERASE Pin.
Memories	Updated text in Embedded Flash Overview.
Peripherals	Updated the table Peripheral Identifiers.
Enhanced Embedded Flash Controller (EEFC)	Updated text in: Write Commands Erase Commands EEFC_FCR register for the FCMD bit
Power Management Controller (PMC)	Corrected the bitfield for the PCKRDY7 bit in the PMC_IMR register.
External Bus Interface (EBI)	Corrected erroneous voltage description.
Quad Serial Peripheral Interface (QSPI)	Corrected the missing bitfield WIDTH in QSPI_IFR.
Timer Counter (TC)	Corrected the Register offset for TC_QIDR.
Electrical Characteristics for SAM V70/V71	Updated the DC Characteristics table Updated the Power Consumption description Updated theFlash Characteristics table in Embedded Flash Characteristics Corrected text and equations under Maximum SPI Frequency for Master Read Mode and Slave Write Mode Updated the SPI Timings section Updated SMC Timings and the sub-sections Read Timings and Write Timings Updated USART SPI Timings
Electrical Characteristics for SAM E70/S70	Updated the DC Characteristics table Updated the Power Consumption description Updated Embedded Flash Characteristics Corrected text and equations under Maximum SPI Frequency for Master Read Mode and Slave Write Mode Updated the SPI Timings section Updated SMC Timings and the sub-sections Read Timings and Write Timings Updated USART SPI Timings Updated SSC Timings section with corrections to Timing Conditions
Schematic Checklist	Updated the schematics in Memory Controllers.

Table 3. Rev. C - 10/2018
Section Name or Type	Update Description
General Updates	PMC - Added missing PCKRDY7, which is missing in the PMC_IER, PMC_IDR and PMC_SR registers. MCAN - Changed reset value for the MCAN_CREL register. AFE - Changed CHNB bit field offset in the AFEC_LCDR register
Package Drawings	Added the following package mechanical drawings: LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm, with wettable flanks

Table 4. Rev. B - 05/2018
Section Name or Type	Update Description
General Updates	Updated “Package and Pinout” and “Electrical Characteristics” sections to fix issues after merging individual data sheets.

Table 5. Rev. A - 04/2018
Section Name or Type	Update Description
General Updates	Updated from Atmel to Microchip style and template Literature number: was changed from the Atmel 44003E to a Microchip DS number Data sheet revision letter restarted to "A" ISBN number added

Table 6. SAM E70/S70/V70/V71 Datasheet Rev. 44003E – Revision History
Date	Changes
12-Oct-16	Removed Preliminary status from the data sheet.
	Renamed instances of Timer Counter (TC) in: - Figure 10-1 “Product Mapping” - Table 12-1 “Real-time Event Mapping List” - Table 14-1 “Peripheral Identifiers”
	Restructured Section 1. ”Description”.
	Table 2-1 “Configuration Summary” : Added Note (3) on USART/UART functionality. Reorganized table notes.
	Table 6-3 “64-lead LQFP Package Pinout” : deleted signal names for pins 50, 51, 53 and 54 for PIO Peripheral D. (now unassigned)
	Table 14-1 “Peripheral Identifiers” : TWIHS0/1 instances read now as I2C-compatible.
	Section 15. ”ARM Cortex-M7” Number of IRQs changed to 74 in Table 15-3 “ARM Cortex-M7 Configuration” and Section 15.4.6.3 ”Interrupt Program Status Register”.
	Section 23. ”Supply Controller (SUPC)” Section 23.4.10 ”Register Write Protection”: in list of protectable registers, removed “System Controller Write Protection Mode Register”.
	Section 24. ”Watchdog Timer (WDT)” Removed references to LOCKMR in Section 24.4 ”Functional Description”, Section 24.5.1 ”Watchdog Timer Control Register” and Section 24.5.2 ”Watchdog Timer Mode Register”. Section 24.5.2 ”Watchdog Timer Mode Register”: corrected access to ‘Read/Write Once’.
	Section 27. ”Real-time Clock (RTC)” Reworked Positive Correction section in Figure 27-5 “Calibration Circuitry Waveforms”.
	Section 30. ”Clock Generator” Updated Section 30.5.2 ”Main RC Oscillator Frequency Adjustment”
	Section 31. ”Power Management Controller (PMC)” Figure 31-1 “General Clock Distribution Block Diagram”: updated PMC_PCR block. Section 31.4 ”Master Clock Controller”: added note concerning fields MDIV and CSS. “Core and Bus Independent Clocks for Peripherals” now Section 31.8 (was Section 32.12). Table 31-1 “Clock Assignments” : added note on PCKx requirements. Section 31.9 ”Peripheral and Generic Clock Controller”: changed title (was “Peripheral Clock Controller”) and updated content regarding generic clock. Section 31.12 ”Programmable Clock Output Controller”: in second paragraph, modified range of selectable Output Signal dividing values from “a power of 2 between 1 and 64” to “1 to 256”. Section 31.17 ”Recommended Programming Sequence”: in Step 8, modified range of PCKx prescaler selectable values from “1, 2, 4, 8, 16, 32, 64” to “1 to 256”. Table 31-4 “Register Mapping” : defined 0x0040_4040 as PMC_OCR reset value; deleted footnote “The reset value depends on factory settings.” Section 31.20.1 ”PMC System Clock Enable Register”, Section 31.20.2 ”PMC System Clock Disable Register” and Section 31.20.3 ”PMC System Clock Status Register”: bit 15 modified to PCK7 (was ‘reserved’). Section 31.20.10 ”PMC Clock Generator PLLA Register”: changed DIVA description for value ‘0’.
cont’d on next page
12-Oct-16	Section 33. ”External Bus Interface (EBI)” Table 33-1 “EBI I/O Lines Description” : added Note (1) on SDCK.
	Section 34. ”SDRAM Controller (SDRAMC)” Section 34.7.3 ”SDRAMC Configuration Register”: in TWO_CS description, added “This feature is not supported when SDR-SDRAM device embeds two internal banks.” Updated description tables for NC and NR fields.
	Section 36. ”DMA Controller (XDMAC)” Table 36-1 “Peripheral Hardware Requests” : replaced line with ‘DACC - Transmit - 30’ by two lines ‘DACC0 - Transmit - 30’ and ‘DACC1 - Transmit - 31’ Added information regarding XDMAC_CC.INITD in Section 36.8 ”XDMAC Software Requirements” and Section 36.9.28 ”XDMAC Channel x [x = 0..23] Configuration Register”. Section 36.9.3 ”XDMAC Global Weighted Arbiter Configuration Register”: replaced “XDMAC scheduler” with “DMAC scheduler” throughout.
	Section 39. ”Ethernet MAC (GMAC)” Section 39.2 ”Embedded Characteristics”: deleted queue sizes (now found in Table 39-5 “Queue Size” ). Section 39.6.3.9 ”Priority Queueing in the DMA”: added Table 39-5 “Queue Size” and updated queue sizes. Section 39.6.15 ”Time Stamp Unit”: changed pin reference from “TIOB11/PD22” to “TIOA11/PD21”. Section 39.6.18 ”Energy-efficient Ethernet Support”: removed all references to Gigabit Ethernet. Updated Section 39.6.19 ”802.1Qav Support - Credit-based Shaping”: added definitions of portTransmitRate and IdleSlope; updated content on queue priority management. Section 39.6.20 ”LPI Operation in the GMAC”: Updated steps for transmit and receive paths. Section 39.8.1 ”GMAC Network Control Register” changed description of NRTSM bit. Section 39.8.107 ”GMAC Received LPI Time” and Section 39.8.109 ”GMAC Transmit LPI Time”: corrected ‘PCLK’ to ‘MCK” in field description. Section 39.8.115 ”GMAC Credit-Based Shaping IdleSlope Register for Queue A” and Section 39.8.116 ”GMAC Credit-Based Shaping IdleSlope Register for Queue B”: updated example for calculation of IdleSlope.
	Section 41. ”Serial Peripheral Interface (SPI)” Section 41.7.4 ”SPI Slave Mode”: added paragraph on SFERR flag. Updated Section 41.7.5 ”Register Write Protection”. Section 41.8.1 ”SPI Control Register”: below register table, added “This register can only be written if the WPCREN bit is cleared in the SPI Write Protection Mode Register.” Section 41.8.6 ”SPI Interrupt Enable Register”, Section 41.8.7 ”SPI Interrupt Disable Register”: below each register table, added “This register can only be written if the WPITEN bit is cleared in the SPI Write Protection Mode Register.” Section 41.8.5 ”SPI Status Register”: added bit SFERR at index 12 and bit description. Section 41.8.10 ”SPI Write Protection Mode Register”: added bit WPITEN at index 1 and bit description. Added bit WPCREN at index 2 and bit description.
12-Oct-16	Section 42. ”Quad Serial Peripheral Interface (QSPI)” Section 42.1 ”Description”: added Note on device support. Section 42.6.5 ”QSPI Serial Memory Mode”: updated text on data transfer constraint. Figure 42-9 “Instruction Transmission Flow Diagram”: corrected typos: --- “Wait for flag QSPI_SR.INSTRE ... “ (was “QSPI_CR“) --- “Wait for flag QSPI_SR.CSR ... “ (was “QSPI_CR“) - Added new instruction: “Read QSPI_SR (dummy read) to clear QSPI_SR.INSTRE and QSPI_SR.CSR“. Updated Figure 42-8 “Instruction Frame”, Figure 42-10 “Continuous Read Mode”, Figure 42-16 “Instruction Transmission Waveform 6”, Figure 42-17 “Instruction Transmission Waveform 7” and Figure 42-19 “Instruction Transmission Waveform 9”.
	Section 46. ”Universal Synchronous Asynchronous Receiver Transceiver (USART)” Section 46.4 ”I/O Lines Description”: removed mention of USART3 as fully equipped with modem signals. Updated Figure 46-27 “RTS Line Software Control when US_MR.USART_MODE = 2” Section 46.7.17 ”USART Channel Status Register”: updated RTSDIS description.
	Section 49. ”Controller Area Network (MCAN)” Section 49.1 ”Description”: updated information on compliance. Updated Table 49-2 “Peripheral IDs” .
	Section 50. ”Timer Counter (TC)” Section 50.6.16.2 ”Input Preprocessing”: removed unit following equation in 3rd paragraph. Added limitation on maximum pulse duration. Section 50.6.16.4 ”Position and Rotation Measurement”: in 3rd paragraph, added “The process must be started by configuring TC_CCR.CLKEN and TC_CCR.SWTRG.” “Detecting a Missing Index Pulse” now Section 50.6.16.6 (was Section 50.6.17). Corrected value of TC_RC0.RC in example in 2nd paragraph. Added Section 50.6.16.7 ”Detecting Contamination/Dust at Rotary Encoder Low Speed”. Section 50.7.16 ”TC Block Mode Register”: added AUTOC at index 18 and bit description. Added MAXCMP at index [29:26] and field description. Updated MAXFILT field description. Section 50.7.17 ”TC QDEC Interrupt Enable Register”, Section 50.7.17 ”TC QDEC Interrupt Enable Register”, Section 50.7.17 ”TC QDEC Interrupt Enable Register” and Section 50.7.17 ”TC QDEC Interrupt Enable Register”: added bit MPE at index 3 and bit description
	Section 51. ”Pulse Width Modulation Controller (PWM)” Throughout, “PWMTRG” and “EXTTRG” renamed to “PWMEXTRG”. Updated Figure 51-1 “Pulse Width Modulation Controller Block Diagram”. Updated section “Recoverable Fault”. Updated Figure 51-16 “Fault Protection”. Section 51.6.7 ”Register Write Protection”: added PWM_IER1, PWM_IDR1, PWM_IER2 and PWM_IDR2 to list of write-protected registers in Register group 1. Section 51-8 ”Register Mapping”: modified offsets for “PWM External Trigger Register 1”, “PWM Leading-Edge Blanking Register 1”, “PWM External Trigger Register 2” and “PWM Leading-Edge Blanking Register 2”. Section 51.7.5 ”PWM Interrupt Enable Register 1”, Section 51.7.6 ”PWM Interrupt Disable Register 1”, Section 51.7.14 ”PWM Interrupt Enable Register 2”, Section 51.7.15 ”PWM Interrupt Disable Register 2”: below each register table, added “This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.”
12-Oct-16	Section 52. ”Analog Front-End Controller (AFEC)” Section 52.5.7 ”Fault Output”: updated section with details on AFEC_TEMPMR and AFEC_TEMPCWR. Section 52.7.2 ”AFEC Mode Register”: updated TRACKTIM description.
	Section 53. ”Digital-to-Analog Converter Controller (DACC)” Table 53-1 “DACC Signal Description” : corrected pin names to VREFP and VREFN (were ADVREFP and ADVREFN).
	Section 54. ”Analog Comparator Controller (ACC)” Table 54-1 “ACC Signal Description” : modified Description for DAC0, DAC1 signals. Section 54.7.7 ”ACC Analog Control Register”: updated HYST definition.
	Section 57. ”Advanced Encryption Standard (AES)” Section 57.2 ”Embedded Characteristics”: replaced “12/14/16 Clock Cycles Encryption/Decryption Processing Time...” with “10/12/14 Clock Cycles Encryption/Decryption Inherent Processing Time...”.
	Section 58. ”Electrical Characteristics” Table 58-3 “DC Characteristics” : removed Note 2 on current injection. Table 58-4 “DC Characteristics” : voltage input level defined for the RST and TEST I/O types. Updated max values for IIL and IIH. Updated Table 58-15 “Typical Current Consumption in Wait Mode” . Table 58-30 “VREFP Electrical Characteristics” : updated V_VREFP parameter values. Added new Table 58-34 “AFE INL and DNL, fAFE Clock =<20 MHz max, IBCTL=10” and Table 58-35 “AFE INL and DNL, fAFE Clock >20 MHz to 40 MHz, IBCTL=11” . Inserted new Table 58-36 “AFE Offset and Gain Error, VVREFP = 1.7V to 3.3V” . Updated Table 58-40 “DAC Static Performances (1)” . Updated Table 58-46 “Static Performance Characteristics” Added Section 58.13.1.10: “USART in Asynchronous Mode”.
	Section 62. ”Ordering Information” Added Note ⁽²⁾ on availability.
	Section 63. ”Errata” Added: - Section 63.1.16 ”Universal Synchronous Asynchronous Receiver Transmitter (USART)”: “Bad frame detection issue” - Section 63.2.4 ”ARM Cortex-M7”: “All issues related to the ARM r1p1 core are described on the ARM site” - Section 63.2.6 ”Inter-IC Sound Controller (I2SC)”: “I2SC first sent data corrupted” - Section 63.2.12 ”Universal Synchronous Asynchronous Receiver Transmitter (USART)”: “Bad frame detection issue” Deleted: - Section 63.1.1 ”AFE Controller (AFEC)”: “AFE max sampling frequency is 1.74 Msps” - Section 63.2.1 ”AFE Controller (AFEC)”: “AFE max sampling frequency is 1.74 Msps”
End

Table 7. SAM E70/S70/V70/V71 Datasheet Rev. 44003D – Revision History
Date	Comments
01-June-16	“Introduction” AFE maximum sampling frequency now 1.7 Msps.
	“Features” Main RC oscillator default frequency changed to 12 MHz. AFE maximum sampling frequency now 1.7 Msps.
	Section 2. “Configuration Summary” Table 2-1 “Configuration Summary”: on QFN64 package, HS USB now supported.
	Table 4-1 “Signal Description List”: updated ‘Comments’ column for for signals PCK0–PCK2, TRACECLK,, URXDx, Timer Counter - TC and for CANTXx. Added comment on Programmable Clock Output for PCK7 and on I2SC for GCLK.
	Table 6-1 “144-lead Package Pinout”: CANRX1 now shown as not available on PD28. Added signal type for I2SC signals. Updated notes (5) and (10).
	Table 6-2 “100-lead Package Pinout”: Added signal type for I2SC signals. Updated notes (5) and (10).
	Table 6-3 “64-lead LQFP Package Pinout”: updated notes (4) and (9).
	Section 7.2.1 “Powerup”: updated equation for minimum VDDCORE slope.
	Table 14-1 “Peripheral Identifiers”: Added IDs 71, 72, 73.
	Section 19. “Bus Matrix (MATRIX)” Section 19.1 “Description”, Section 19.2 “Embedded Characteristics”: number of masters changed to 13. Table 19-1 “Bus Matrix Masters” and Table 19-3 “Master to Slave Access”: added Master 12: Cortex-M7. Table 19-3 “Master to Slave Access”: changed access for Master 0/Slave 6. Added Section 19.3.6 “Configuration of Automatic Clock-off Mode”. Table 19-4 “Register Mapping”: added register CCFG_DYNCFG at offset 0x011C and register CCFG_PCCR at offset 0x0118. Added Section 19.4.8 “Peripheral Clock Configuration Register”. Added Section 19.4.9 “Dynamic Clock Gating Register”.
	Section 21. “Chip Identifier (CHIPID)” Updated Table 21-1 “SAM V71 Chip ID Registers”. Added notes (1) and (2).
	Section 23. “Supply Controller (SUPC)” Section 23.4.3 “Core Voltage Regulator Control/Backup Low-power Mode”: removed information on Backup mode entry via WFE. Corrected ONREG polarity. Figure 23-6 “Raising the VDDIO Power Supply”: removed Flash frequency in Note. Section 23.4.10 “Register Write Protection”: deleted Section 23.5.7 “Supply Controller Wakeup Inputs Register” from list of write-protected registers. Added Section 23.5.9 “System Controller Write Protection Mode Register”.
cont’d
01-June-16	Section 24. “Watchdog Timer (WDT)” Section 24.4 “Functional Description”: Added detail on LOCKMR bit in paragraph starting “WDT_MR can be written...” Modified paragraph starting with “The reload of the WDT must occur...”. Table 24-1 “Register Mapping”: modified Access for Section 24.5.2 “Watchdog Timer Mode Register”. Section 24.5.1 “Watchdog Timer Control Register”: LOCKMR bit now at index 4 (was ‘reserved’). Section 24.5.2 “Watchdog Timer Mode Register”: modified access and updated Note (1).
	Section 25. “Reinforced Safety Watchdog Timer (RSWDT)” Updated Figure 25-1 “Reinforced Safety Watchdog Timer Block Diagram”.
	Section 26. “Reset Controller (RSTC)” ‘Slow crystal’ changed to ‘32.768 kHz’ throughout. Updated figures: - Figure 26-1 “Reset Controller Block Diagram” - Figure 26-3 “General Reset Timing Diagram” - Figure 26-4 “Watchdog Reset Timing Diagram” - Figure 26-5 “Software Reset Timing Diagram”” - Figure 26-6 “User Reset Timing Diagram” Added Note to Section 26.4.1 “Overview”. Updated Section 26.4.3.3 “Watchdog Reset”: Replaced “is set” with “is written to 1” and “is reset” with “is written to 0”. Section 26.5.3 “RSTC Mode Register”: updated URSTIEN description.
	Section 27. “Real-time Clock (RTC)” Updated Section 27.5.6 “Updating Time/Calendar”.
	Section 29. “SDRAM Controller (SDRAMC)” Section 29.5.1 “SDRAM Device Initialization”: updated first step.
cont’d
01-June-16	Section 31. “Clock Generator” Oscillator naming changed throughout to: - Slow RC oscillator - 32.768 kHz crystal oscillator - Main RC oscillator - Main crystal oscillator Main RC oscillator default frequency changed to 12 MHz throughout. Updated Figure 31-1 “Clock Generator Block Diagram”. Section 31.4 “Slow Clock”: changed ‘powered up’ to ‘powered’. Updated Section 31.4.1 “Slow RC Oscillator (32 kHz typical)”. Section 31.4.2 “32.768 kHz Crystal Oscillator”: identified default state. Updated details on XIN32 and XOUT32. Deleted sentence on external capacitors and figure “Typical 32.768 kHz Crystal Oscillator Connection”. Updated paragraph on selecting the source of Slow clock. Updated Figure 31-2 “Main Clock (MAINCK) Block Diagram”. Added Figure 31-3 “Main Frequency Counter Block Diagram”. Section 31.5.1 “Main RC Oscillator”: added Note in paragraph on output frequency. Corrected two occurrences of ‘Main clock’ to ‘Main RC oscillator’. Deleted recommendation to disable oscillators under certain conditions. Moved paragraph on adjusting Main RC osc frequency to Section 31.5.2 “Main RC Oscillator Frequency Adjustment”. Section 31.5.2 “Main RC Oscillator Frequency Adjustment”: updated 1st and last paragraphs. Deleted some redundant content. Section 31.5.3 “Main Crystal Oscillator”: updated information on programming startup time. Section 31.5.4 “Main Clock Source Selection”: updated list of selectable main clock sources. Section 31.5.6 “Main Frequency Counter” renamed section (was “Main Clock Frequency Counter”). Updated 1st paragraph. Section 31.5.7 “Switching Main Clock between the RC Oscillator and Crystal Oscillator” now part of Section 31.5.6 “Main Frequency Counter”. Section 31.6 now titled ”PLLA Clock” (was “Divider and PLL Block”). Section 31.6.1 “Divider and Phase Lock Loop Programming”: updated information on changing MAINCK characteristics. Section 31.7 now titled ”UTMI PLL Clock” (was UTMI Phase Lock Loop Programming). Added paragraph on multiplying factors.
cont’d
01-June-16	Section 32. “Power Management Controller (PMC)” Main RC oscillator default frequency changed to 12 MHz throughout. Updated Section 31.1 “Description”. Section 32.2 “Embedded Characteristics”: updated bullet on Clock sources, Peripheral clocks and on Generic clocks. Deleted bullet on Embedded Trace Macrocell (ETM). Updated Figure 32-1 “General Clock Distribution Block Diagram”. Updated Section 32.4 “Master Clock Controller”. Table 32-1 “Clock Assignment”: added PCK7 assignment. Section 32.13 “Fast Startup”: updated processor restart period. Deleted sequence “Prior to instructing the device to enter Wait mode...”. Section 32.20.4 “PMC Peripheral Clock Enable Register 0”, Section 32.20.5 “PMC Peripheral Clock Disable Register 0” and Section 32.20.6 “PMC Peripheral Clock Status Register 0”: added bits PIDx at index[15:9] (were ‘reserved’). Section 32.20.8 “PMC Clock Generator Main Oscillator Register”: updated MOSCRCF bit description. Section 32.20.9 “PMC Clock Generator Main Clock Frequency Register”: updated CCSS bit description. Section 32.20.14 “PMC Interrupt Enable Register”, Section 32.20.15 “PMC Interrupt Disable Register”, Section 32.20.16 “PMC Status Register” and Section 32.20.17 “PMC Interrupt Mask Register”: added bits PCKRDYx at index[14:11] (were ‘reserved’). Updated Section 32.15 “Main Crystal Oscillator Failure Detection”. Updated Figure 32-5 “Clock Failure Detection Example”. Section 32.16 “32.768 kHz Crystal Oscillator Frequency Monitor”: updated 1st paragraph. Added detail on effects of modifying trimming values of Main RC oscillator. Section 32.20.8 “PMC Clock Generator Main Oscillator Register”: updated description of MOSCRCF field for value ‘0’. Deleted note from CFDEN description. Section 32.20.16 “PMC Status Register”: updated FOS description.
	Section 37. “Image Sensor Interface (ISI)” Updated “12-bit Grayscale Mode” . Section 37.6.1 “ISI Configuration 1 Register”: added bit GRAYLE at index 5 and bit description. Section 37.6.12 “ISI Interrupt Enable Register”, Section 37.6.13 “ISI Interrupt Disable Register”: changed access from “Read/Write” to “Write-only”. Section 37.6.14 “ISI Interrupt Mask Register”: changed access from “Read/Write” to “Read-only”.
	Section 38. “USB High-Speed Interface (USBHS)” Section 38.6.1 “General Control Register”: added bit UID at index 24 and bit description.
cont’d
01-June-16	Section 39. “Ethernet MAC (GMAC)” Throughout: Number of queues increased to 6 (was 3). Updated Section 39.5.3 “Interrupt Sources”: number of interrupt sources increased to 6 (was 3). Table 39-1 “GMAC Connections in Different Modes”: added table Note on GTXCK. Added Section 39.6.18 ”Energy-efficient Ethernet Support” and Section 39.6.20 ”LPI Operation in the GMAC”. Section 39.7.1.2 “Receive Buffer List” and Section 39.7.1.3 “Transmit Buffer List”: added note on queue pointer intilaization at end of sections . Table 39-17, “Register Mapping”: added registers at offsets 0x270 to 0x27C. Section 39.8.1 ”GMAC Network Control Register”: added bit 19: TXLPIEN: Enable LPI Transmission (was ‘reserved’). Added bit description. Section 39.8.3 ”GMAC Network Status Register”: added bit 7: RXLPIS: LPI Indication (was ‘reserved’). and bit description. Added bit 27: RXLPISBC: Receive LPI indication Status Bit Change, and bit description and bit 29: TSUTIMCOMP: TSU timer comparison interrupt, and bit description in - Section 39.8.10 ”GMAC Interrupt Status Register” - Section 39.8.11 ”GMAC Interrupt Enable Register” - Section 39.8.12 ”GMAC Interrupt Disable Register” - Section 39.8.13 ”GMAC Interrupt Mask Register”. Section 39.8.13 ”GMAC Interrupt Mask Register”: added bit 26, SRI, and bit 28, WOL, and bit descriptions. Added following sections: Section 39.8.106 ”GMAC Received LPI Transitions” Section 39.8.107 ”GMAC Received LPI Time” Section 39.8.108 ”GMAC Transmit LPI Transitions” Section 39.8.109 ”GMAC Transmit LPI Time” Section 39.8.111 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x” and Section 39.8.112 “GMAC Receive Buffer Queue Base Address Register Priority Queue x”: changed sentence on register initialization.
	Section 40. “High Speed Multimedia Card Interface (HSMCI)” Section 40.14.2 “HSMCI Mode Register”: modified CLKDIV field description.
	Section 41. “Serial Peripheral Interface (SPI)” Modified transmission condition description in Section 41.7.3 “Master Mode Operations”. Removed TXFCLR, RXFCLR, FIFOEN and FIFODIS bits in Section 41.8.1 “SPI Control Register”.
cont’d
01-June-16	Section 42. “Quad SPI Interface (QSPI)” Section 42.2 “Embedded Characteristics”: added bullet on Single Data Rate and Double Data Rate modes. Figure 42-2 “QSPI Transfer Format (QSPI_SCR.CPHA = 0, 8 bits per transfer)” and Figure 42-3 “QSPI Transfer Format (QSPI_SCR.CPHA = 1, 8 bits per transfer)””: modified NSS to QCS. Section 42.7.2 “QSPI Mode Register”: updated CSMODE description. Section 42.7.5 “QSPI Status Register”: updated descriptions of bits CSR and INSTRE.
	Section 43. “Two-wire Interface (TWIHS)” Updated Figure 43-1 “Block Diagram”. Section 43.6.3.9 “SMBus Mode”: deleted bullet on SMBALERT. Section 43.6.5.6 “SMBus Mode”: deleted bullet on SMBALERT. Section 43.7.5 “TWIHS Clock Waveform Generator Register”: Bit 20 now ‘reserved’ (was CKSRC: Transfer Rate Clock Source). HOLD field extended to 6 bits.
	Section 44. “Synchronous Serial Controller (SSC)” in Figure 44-19 “Interrupt Block Diagram”: renamed RXSYNC to RXSYN; renamed TXSYNC to TXSYN.
	Section 45. “Inter-IC Sound Controller (I2SC)” Throughout: In text, tables and figures, pin names changed to: - I2SC_MCK - I2SC_CK - I2SC_WS - I2SC_DI - I2SC_DO Updated Figure 45-1 “I2SC Block Diagram”. Section 45.6.1 “Initialization”: modified register name from CCFG_I2SCLKSEL to CCFG_PCCR. Section 45.6.5 “Serial Clock and Word Select Generation”: updated paragraph on I2SC input clock selection in Master mode. Updated Figure 45-3 “I2SC Clock Generation”. Section 45.8.2 “I2SC Mode Register”: updated MODE bit description for value ‘1’. Updated IMCKDIV and IMCKMODE field descriptions.
	Section 46. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Section 46.2 “Embedded Characteristics”: added bullet “Optimal for Node-to-Node Communication (no embedded digital line filter)” to LON Mode features. Section 46.6.3.11 “Receiver Timeout”: deleted redundant paragraphs on STTTO and RETTO. Section 46.6.4 “ISO7816 Mode”: corrected USART_MODE value for prototcol T = 1. Section 46.6.10 “LON Mode”: added information on node-to-node communication. Section 46.7.3 “USART Mode Register”: updated USART_MODE description to include LIN mode support.
cont’d
01-June-16	Section 49. “Controller Area Network (MCAN)” Throughout: Renamed Fast Bit TIming and Prescaler Register to Data Bit TIming and Prescaler Register (MCAN_DBTP). Renamed field FBRP to DBRP and updated description. Updated descriptions of DSJW, DTSEG2 and DTSEG1. Added Section 49.4.5 “Timestamping”. Changed ‘Baud’ to ‘Bit’ in: - Section 49.5.3 “Timeout Counter”: in ‘Note’. - Section 49.6.4 “MCAN Data Bit Timing and Prescaler Register”: DBRP field description. - Section 49.6.8 “MCAN Nominal Bit Timing and Prescaler Register” NBRP field description. Updated Section 49.5.1.3 “CAN FD Operation”. Renamed section Transceiver Delay Compensation to Transmitter Delay Compensation (Section 49.5.1.4). Changed NTSEG1 to TSEG1. Updated content. Section 49.5.1.5 “Restricted Operation Mode”: added ‘Note’. Updated Figure 49-5 “Standard Message ID Filter Path” and Figure 49-6 “Extended Message ID Filter Path”. Section 49.6.7 “MCAN CC Control Register”: added bit NISO. Updated descriptions of FDOE, BRSE, PXHD and EFBI. Section 49.6.9 “MCAN Timestamp Counter Configuration Register”: updated TSS description. Section 49.6.10 “MCAN Timestamp Counter Value Register”: updated TSC description. Section 49.6.20 “MCAN Global Filter Configuration”: added some details on register description. Updated ANFE and ANFS field descriptions. Section 49.6.21 “MCAN Standard ID Filter Configuration” and Section 49.6.22 “MCAN Extended ID Filter Configuration”: added some details on register description. Section 49.6.24 “MCAN High Priority Message Status”: updated MSI description for value ‘1’.
01-June-16	Section 50. “Timer Counter (TC)” Throughout: Replaced TIOA, TIOB, TCLK with TIOAx, TIOBx, TCLKx. Reformatted and renamed Table 50-2 “Channel Signal Description”. Table 50.6.3 “Clock Selection”: updated notes (1) and (2). Updated Section 50.6.16.4 “Position and Rotation Measurement”. Added Section 50.6.17 “Detecting a Missing Index Pulse”.
cont’d
01-June-16	Section 52. “Analog Front-End Controller (AFEC)” Section 52.2 “Embedded Characteristics”: deleted bullet on conversion rate (redundant with Electrical Characteristics) Section 52.6.1 “Analog Front-End Conversion”: updated and changed clock frequency range. Updated formula to calculate AFE conversion time. Section 52.6.3 “Conversion Resolution”: added Note. Section 52.6.6 “Conversion Triggers”: added detail on effects of delay variation. Section 52.6.11 “Input Gain and Offset”: updated information on AOFF field. Section 52.6.12 “AFE Timings”: updated Warning and deleted paragraph on settling time. Section 52.6.15 “Automatic Error Correction”: - modified the description of Gs and value (now 15, was 11). - modified the formula given to obtain the final conversion result after error correction. - added details on OFFSETCORR and GAINCORR fields. - deleted definitions of unused terms ‘ConvValue’ and ‘Resolution’ - added Figure 7-14 “AFE Digital Signal Processing”. Section 52.7.2 “AFEC Mode Register”: updated descriptions of fieldsTRACKTIM and TRANSFER. Section 52.7.18 “AFEC Channel Selection Register”: updated CSEL bit description. Section 52.7.20 “AFEC Channel Offset Compensation Register”: added note on configuration of AOFF.
	Section 58. “Electrical Characteristics” Added Table 58-2 “Recommended Thermal Operating Conditions”. Updated Table 58-3 “DC Characteristics”. Updated Table 58-31 “AFE Timing Characteristics”. Modified AFEC_ACR.IBCTL value in Note (1) of Table 58-31 “AFE Timing Characteristics” and in Section 58.8.1.2 “ADC Bias Current”. Table 58-38 “Number of Tau:n”: deleted bullets on calculated tracking time. Updated Table 58-41 “Temperature Sensor Characteristics”. Table 58-52 “I/O Characteristics”: updated VDDIO for FreqMax1. Section 58.13.1.5 “QSPI Characteristics”: updated comments in “Master Read Mode” Corrected CKx typo in Figure 58-36 “SSC Transmitter, TK and TF in Input”.
	Section 59. “Mechanical Characteristics” All sections: Modified JEDEC classification to J-STD-609 from JESD97.
	Section 60. “Schematic Checklist” Added note following Figure 60-4 “Schematic Example with a 16 Mb/16-bit SDRAM (1)”.
cont’d
01-June-16	Section 62. “Ordering Information” Updated Table 62-1 “Ordering Codes for SAM V71 Devices”.
01-June-16	Section 63. “Errata” Added - Section 63.1.1 “AFE Controller (AFEC)”: “AFE max sampling frequency is 1.74 Msps” and “Changing AFEC_COCR.AOFF during conversions is not safe” . - Section 63.1.5 “Boundary Scan Mode”: “Boundary Scan Mode” - Section 63.1.8 “Ethernet MAC (GMAC)”: “Error in number of queues” - Section 63.1.10 “Master CAN-FD Controller (MCAN)”: “Timestamping issue with external clock” - Section 63.1.11 “Parallel Input/Output (PIO)”: “PIO line configuration for AFEC and DACC analog inputs” - Section 63.1.12 “Power Management Controller (PMC)”: “PMC_OCR does not report the Main RC oscillator manufacturing calibration value” - Section 63.1.14 “SDRAM Controller (SDRAMC)”: “Limitation to scrambling/unscrambling use” Added Section 63.2 “Revision B Parts”.
End

Table 8. SAM E70/S70/V70/V71 Datasheet Rev. 44003C – Revision History
Date	Changes
08-Feb-16	Added TFBGA144 package to features, configuration summary, package and pinout, mechanical drawings, ordering information and AMR.
	Deleted LFBGA144 package from features, configuration summary, package and pinout, mechanical drawings, ordering information and AMR.
	Deleted TFBGA64 package from features, configuration summary, package and pinout, mechanical drawings, ordering information and AMR.
	Deleted QFN64 package from features, configuration summary, package and pinout, mechanical drawings, ordering information and AMR.
	Added “Introduction”. “Features”: Updated sections: Memories, Low-Power Features, QSPI, e.MMC and DACC. Added I2SC. Changed ADC to AFE. Corrected number of I/O lines. Change voltage. Table 2-1 “Configuration Summary”: updated table. Added I2SC. Table 4-1 “Signal Description List“: added signals GNDPLL, GNDPLLUSB, GNDANA, GNDUTMI. Added I2SC. Removed redundant content from column “Comments”.
	Section 6. “Package and Pinout”: added information on reset state in pinout tables. Table 6-1 “144-lead Package Pinout”: updated table. Changed I/O type for all SDA10 to GPIO_AD. Added I2SC pins. Table 6-2 “100-lead Package Pinout”: updated table. Changed I/O type for all SDCK to GPIO_CLK. Added I2SC pins.
	Section 7. “Power Considerations” Updated Table 7-1 “Power Supplies”. Section 7.2 ”Power Constraints”: removed bullet on USB. Section 7.2.1 ”Power-up”: added constraint regarding overcurrent. Section 7.2.2 ”Power-down”: added constraint regarding overcurrent. Updated Table 7-2 “Low-power Mode Configuration Summary”.
	Section 8. “Input/Output Lines” Removed redundant Section 6.3. TST Pin (already in Section 16. “Debug and Test Features”). Updated Section 8.4 “ERASE Pin”.
	Section 10. ”Product Mapping” Updated Figure 9-4, “SAM V71 Product Mapping” with I2SC.
	Section 11. “Memories” Updated Section 11.1.2 “Tightly Coupled Memory (TCM) Interface” and Section 11.1.4 “Backup SRAM”. Updated Section 11.1.5.6 “Unique Identifier”.
	Section 12. “Event System” Updated Table 12-1 “Real-time Event Mapping List” with I2SC.
	Section 13. “System Controller” Section 13.1 “System Controller and Peripherals Mapping”: removed sentence on bit band.
	Section 14. “Peripherals” Updated Table 14-1 “Peripheral Identifiers”.
	Section 15. “ARM Cortex-M7 Processor” Section 15-3 “ARM Cortex-M7 Configuration”: changed number of IRQ priority levels.
08-Feb-16	Section 16. “Debug and Test Features” Removed redundant Section 15.7.2. NRST Pin and Section 15.7.3. ERASE Pin (already in Section 8. “Input/Output Lines”). Removed references to Embedded Trace Buffer (ETB). Section 16.7.8 ”IEEE1149.1 JTAG Boundary Scan”: updated condtions to enable boundary scan.
	Section 18. “Fast Flash Programming Interface (FFPI)” Table 18-1 “Signal Description List“: updated XIN information. Deleted comment for XIN. Section 18.3 “Parallel Fast Flash Programming”, Figure 18-1, “16-bit Parallel Programming Interface”: changed input source for XIN. Section 18.3.3 “Entering Parallel Programming Mode”: deleted note on device clocking. Reworded steps 2 and 3.
	Section 19. “Bus Matrix (MATRIX)” Table 19-4 “Register Mapping”: corrected reset values for MATRIX_PRASx and MATRIX_PRBSx registers. In Section 19.4.8 “SMC NAND Flash Chip Select Configuration Register”: - added warning to bit description SMC_NFCS1. - changed SDRAMEN bit description and added warning.
	Section 22. “Enhanced Embedded Flash Controller (EEFC)” Updated Section 22.2 “Embedded Characteristics”. Added Figure 22-1, “Flash Memory Areas”. Section 22.4.3.6 “Calibration Bit”: updated oscillators that are calibrated in production. Section 22.4.3.7 “Security Bit Protection”: added detail on ETM.
	Section 23. “Supply Controller (SUPC)” Figure 23-2, “Separate Backup Supply Powering Scheme”: updated figure and corrected min voltage in note on ADC/DAC/ACC.
	Section 24. “Watchdog Timer (WDT)” Section 24.1 “Description”: Replaced “Idle mode” with “Sleep mode (Idle mode)”. Section 24.4 “Functional Description”: replaced “Idle mode” with “Sleep mode” Section 24.4 “Functional Description”, Section 24.5.2 “Watchdog Timer Mode Register”: modified information on WDDIS bit setting to read “When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified.” Section 24.5.1 “Watchdog Timer Control Register”: added note on modification of WDT_CR values.. Section 24.5.2 “Watchdog Timer Mode Register”: added Note (2) on modification of WDT_MR values.
	Section 25. “Reinforced Safety Watchdog Timer (RSWDT)” Section 25.5.2 “Reinforced Safety Watchdog Timer Mode Register”: bit 14 now reserved.
	Section 26. “Reset Controller (RSTC)” Section 26.4.3.1 “General Reset”: removed reference to NRSTB. Table 26.5 “Reset Controller (RSTC) User Interface”: updated reset value for RSTC_MR.
	Section 27. “Real-time Clock (RTC)” Updated Section 27.5.7 “RTC Accurate Clock Calibration”. Figure 27-4, “Calibration Circuitry Waveforms”: corrected two instances of “3,906 ms” to “3.906 ms”. Table 27-2 “Register Mapping”: corrected reset for RTC_CALR. Added offset 0xCC as reserved. Added RTC_WPMR at offset 0xE4 Section 27.6.1 “RTC Control Register”: updated descriptions of value ‘0’ for bits UPDTIM and UPDCAL. Added Section 27.6.13 “RTC Write Protection Mode Register”. Added write protection for Section 27.6.1 “RTC Control Register”, Section 27.6.2 “RTC Mode Register”, Section 27.6.5 “RTC Time Alarm Register” and Section 27.6.6 “RTC Calendar Alarm Register”.
	Section 30. “General Purpose Backup Registers (GPBR)” Corrected total size of backup registers.
08-Feb-16	Section 31. “Clock Generator” Section 31.2 “Embedded Characteristics”: updated bullet on embedded RC oscillator. Figure 31-3, “Main Clock Block Diagram”: renamed “3-20 MHz Crystal or Ceramic Resonator Oscillator” to “Main Crystal or Ceramic Resonator Oscillator”. Renamed “3-20 MHz Oscillator Counter” to “Main Oscillator Counter”. Section 31.5.1 “Embedded 4/8/12 MHz RC Oscillator”: changed last paragraph beginning “The user can adjust the value...”. Section 31.5.4 ”Main Clock Source Selection”: added that the RC oscillator must be selected for Wait mode. Updated Section 31.5.6 “Main Clock Frequency Counter”. Updated Section 31.5.7 “Switching Main Clock between the RC Oscillator and Crystal Oscillator”. Updated Section 31.6.1 “Divider and Phase Lock Loop Programming” with paragraph on correct programming of the multiplication factor of the PLL. Section 31.7 ”UTMI Phase Lock Loop Programming”: deleted sentence on crystal requirements for USB.
	Section 32. “Power Management Controller (PMC)” Section 32.1 ”Description”: corrected list of oscillators that can be trimmed by software. Section 32.2 ”Embedded Characteristics”: updated bullet on Peripheral Clocks. Added bullet on generic clock. Updated figure Figure 32-1, “General Clock Block Diagram”: replaced “SysTick” with “External SysTick Clock”. Added GCLKx in PMC_PCR block. Updated Section 32.8 ”Peripheral Clock Controller”. Updated Section 32.12 “Core and Bus Independent Clocks for Peripherals”. Added Step 5 and WARNING in Section 32.13 “Fast Startup”. Updated Section 32.15 “Main Clock Failure Detection”. Section 32.17 “Programming Sequence”: in Step 7., modified sub-steps (c) and (e). Section 32.19 “Register Write Protection”: added PMC Clock Generator Main Clock Frequency Register to list of write-protected registers. Table 32-4 “Register Mapping”: modified Reset for PMC_OCR; replaced by note. Added PMC_PMMR at offset 0x0130. Section 32.20.3 ”PMC System Clock Status Register”: added HCLKS at bit 0. Section 32.20.9 “PMC Clock Generator Main Clock Frequency Register”: updated MAINF bit description. Section 32.20.17 “PMC Interrupt Mask Register”: added missing bits PCKRDY3–PCKRDY6 (bits 11 to 14). Section 32.20.26 ”PMC Peripheral Control Register”: added GCLKEN, GCLKDIV, DIV and GCLKCSS bits/fields and descriptions. Corrected maximum PID number to 127. Added missing bits PCKRDY3–PCKRDY6 (bits 11 to 14).: updated PID field description. Deleted DIV field from register table; bits 16 and 17 now reserved. Deleted DIV description. Added Section 32.20.35 “PLL Maximum Multiplier Value Register”.
	Section 33. “Parallel Input/Output Controller (PIO)” Deleted section “Keypad Controller” and all related registers.
	Section 34. “External Bus Interface (EBI)” Added NAND Flash support on NCS0/1/2 (was NCS3 only). Figure 34-1, “Organization of the External Bus Interface”: Removed DQS from block diagram. Section 34.5.3.4 “NAND Flash Support”: changed NCS3 address space.
	Section 29. “SDRAM Controller (SDRAMC)” Updated Step 1. and Step 4. to Step 9. in Section 29.5.1 “SDRAM Device Initialization”. Section 29.6.5.1 “Self-refresh Mode”: added Note. Section 29.7.3 “SDRAMC Configuration Register”: corrected CAS field configuration values.
08-Feb-16	Section 35. “Static Memory Controller (SMC)” Section 35.7.3 “NAND Flash Support”: removed reference to NCS3. Updated Figure 35-5, “NAND Flash Signal Multiplexing on SMC Pins” and added Note 1 below the figure. Section 35.10 “Scrambling/Unscrambling Function”: added details on access for SMC_KEY1 and SMC_KEY2 registers. In Table 35-10 “Register Mapping” and register table sections: SMC OCMS Mode Register now ”“SMC Off-Chip Memory Scrambling Register”. SMC OCMS Key1 Register now ”“SMC Off-Chip Memory Scrambling Key1 Register”. SMC OCMS Key2 Register now “SMC Off-Chip Memory Scrambling Key2 Register”. Section 35.16.5 “SMC Off-Chip Memory Scrambling Register”: corrected bits 8 to 11 to ‘CSxSE’ (were reserved). Section 35.16.6 “SMC Off-Chip Memory Scrambling Key1 Register” and Section 35.16.7 “SMC Off-Chip Memory Scrambling Key2 Register”: added Note (1) to clarify Write-once access.
	Section 36. “DMA Controller (XDMAC)” Updated TC peripheral names and added I2SC in Table 36-1 “Peripheral Hardware Requests”. Section 36.2 “Embedded Characteristics”: added FIFO size. Updated Figure 36-1, “DMA Controller (XDMAC) Block Diagram”. Section 36.5.4.1 “Single Block With Single Microblock Transfer”: in Step 6, deleted sub-step to activate a secure channel. Table 36-3 “Register Mapping“: corrected access of XDMAC_GTYPE, XDMAC_GWAC, XDMAC_CIM. Section 36.9.6 “XDMAC Global Interrupt Mask Register”: corrected access to Read-only. Section 36.9.28 “XDMAC Channel x [x = 0..23] Configuration Register”: bit 5 now reserved (was PROT). Deleted PROT bit description. Updated PERIF field description. Modified INITD bit description.
	Section 38. “USB High-Speed Interface (USBHS)” Table 38-1 “Description of USB Pipes/Endpoints”: corrected value in ‘High Bandwidth’ column for Pipe/Endpoint 1. Added Section 38.4.1 “I/O Lines”. Updated Figure 38-2, “General States”. Updated Section 38.5.3.3 “Device Detection” and added Note on VBUS supply. Section 38.6.1 “General Control Register”: added bit 8, VBUSHWC. Section 38.6.4 “General Status Set Register”: added bit 9, VBUSRQS. Section 38.6.12 “Device Endpoint Register”: bit 9 changed from ‘reserved’ to EPEN9. Bit 25 changed from ‘reserved’ to EPRST9. Bits 10 and 11 now reserved in registers: - Section 38.6.6 “Device Global Interrupt Status Register” - Section 38.6.9 “Device Global Interrupt Mask Register” - Section 38.6.10 “Device Global Interrupt Disable Register” - Section 38.6.11 “Device Global Interrupt Enable Register” - Section 38.6.32 “Host Global Interrupt Status Register” - Section 38.6.35 “Host Global Interrupt Mask Register” - Section 38.6.36 “Host Global Interrupt Disable Register” - Section 38.6.37 “Host Global Interrupt Enable Register”
08-Feb-16	Section 39. “Ethernet MAC (GMAC)” Updated Section 39.1 “Description”. Section 39.5.2 “Power Management”: deleted reference to PMC_PCER. Section 39.5.3 “Interrupt Sources”: deleted reference to ‘Advanced Interrupt Controller’. Replaced by ‘interrupt controller’. Added information on interrupt sources and priority queues. Section 39.6.14 “IEEE 1588 Support”: Removed reference to ‘output pins’ in 2nd paragraph. Deleted reference to GMAC_TSSx. Section 39.6.15 “Time Stamp Unit” added information on GTSUCOMP signal in last paragraph. Updated register index range for: - Section 39.8.106 “GMAC Interrupt Status Register Priority Queue x” - Section 39.8.107 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x” - Section 39.8.108 “GMAC Receive Buffer Queue Base Address Register Priority Queue x” - Section 39.8.109 “GMAC Receive Buffer Size Register Priority Queue x” - Section 39.8.115 “GMAC Interrupt Enable Register Priority Queue x” - Section 39.8.116 “GMAC Interrupt Disable Register Priority Queue x” - Section 39.8.117 “GMAC Interrupt Mask Register Priority Queue x” Section 39.8.117 “GMAC Interrupt Mask Register Priority Queue x”: inverted bit value definitions (‘0’ means enabled, ‘1’ means disabled.
	Section 41. “Serial Peripheral Interface (SPI)” Section 41.8.1 “SPI Control Register”: added bits FIFODIS, FIFOEN, RXFCLR, TXFCLR and REQCLR.
	Section 42. “Quad SPI Interface (QSPI)” Section 42.7.2 “QSPI Mode Register”: updated equations and NBBITS description. Section 42.7.5 “QSPI Status Register”: updated RDRF, TDRE, TXEMPTY, and OVRES field descriptions. Section 42.7.9 “QSPI Serial Clock Register”: updated equations. Section 42.7.12 “QSPI Instruction Frame Register”: updated INSTEN bit description.
	Section 43. “Two-wire Interface (TWIHS)” Section 43.6.3.4 “Master Transmitter Mode” and “Read Sequence”: added sentence on clearing TXRDY flag. Section 43.6.5.7 “High-Speed Slave Mode”: updated 11-MHz limit information. Updated Section 43.6.7 “Register Write Protection”. Updated Section 43.7.1 “TWIHS Control Register”: added bit FIFODIS, FIFOEN, LOCKCLR and THRCLR.
	Added Section 45. “Inter-IC Sound Controller (I2SC)”.
08-Feb-16	Section 46. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Added descriptions of Modem mode and ISO7816 mode throughout. Updated Section 46.1 “Description” and Section 46.2 “Embedded Characteristics”. Table 46-1 “I/O Line Description“ updated and added lines RI, DSR, DCD, and DTR. Section 46.6.1 “Baud Rate Generator”: corrected value in “The frequency of the signal provided on SCK must be at least...” Updated Figure 46-2, “Baud Rate Generator”. “Baud Rate Calculation Example”, corrected formula. Section 46.6.1.2 “Fractional Baud Rate in Asynchronous Mode” and Section 46.7.23 “USART Baud Rate Generator Register”: added warning “When the value of field FP is greater than 0...” Updated Figure 46-3, “Fractional Baud Rate Generator”. Section 46.6.1.3 “Baud Rate in Synchronous Mode or SPI Mode”: corrected formula. Corrected external clock frequency. Corrected SCK maximum frequency. Added Section 46.6.4 ”ISO7816 Mode”. Inserted new Figure 46-27, “RTS Line Software Control when USART_MR.USART_MODE = 2”. Section 46.6.3.4 “Manchester Decoder”: corrected “MANE flag” with “MANERR” flag. Added Section 46.6.7 “Modem Mode”. Section 46.6.8.5 “Character Transmission”: added content to 1st paragraph. Corrected occurrences of RTSEN to RCS, RTSDIS to FCS. Section 46.6.9.8 “Slave Node Synchronization”: updated bullet on oversampling. Updated Figure 46-42, “Slave Node Synchronization”. Section 46.7.1 “USART Control Register”: added bits/fields RSTIT, RSTNACK, DTREN and DTRDIS. Updated RTSDIS bit description. Section 46.7.3 “USART Mode Register”: added bits/fields MAX_ITERATION, INVDATA, DSNACK, INACK, MSBF. Updated USART_MODE field description table. Section 46.7.5 “USART Interrupt Enable Register”, Section 46.7.9 “USART Interrupt Disable Register”, Section 46.7.13 “USART Interrupt Mask Register”: added bits ITER, NACK, RIIC, DSRIC, and DCDIC. Section 46.7.17 “USART Channel Status Register”: added bits ITER, NACK, RIIC, DSRIC, DCDIC, DSR, and DCD. Section 46.7.23 “USART Baud Rate Generator Register”: updated CD field description. Added Section 46.7.27 “USART FI DI RATIO Register” and Section 46.7.29 “USART Number of Errors Register”.
	Section 49. “Controller Area Network (MCAN)” Replaced ‘HCLK’ and ‘m_can_hclk’ by ‘peripheral clock’. Replaced ’can_clk’ by ‘CAN core clock’. Replaced ‘tcan_clk’ by ‘tcore clock’. Section 49.4.2 “Power Management”: added recommendations on clock frequencies. Section 49.5.7 “Message RAM”: deleted sentence on storage constraints. Section 49.5.7.5 “Standard Message ID Filter Element”: updated description of SFID2[5:0]. Section 49.5.7.6 “Extended Message ID Filter Element”: updated description of EFID2[5:0]. Added Section 49.6.1 “MCAN Core Release Register” and Section 49.6.2 “MCAN Endian Register” and updated Table 49-13 “Register Mapping“. Section 49.6.4 “MCAN Fast Bit Timing and Prescaler Register”: updated FSJW, FTSEG2 and FSTEG1 field description: t_{core clock} now t_q Section 49.6.8 “MCAN Bit Timing and Prescaler Register”: updated SJW, TSEG2, TSEG1 and BRP field descriptions: t_{core clock} now t_q
	Section 50. “Timer Counter (TC)” Added important note in Section 50.7.6 “TC Counter Value Register”, Section 50.7.7 “TC Register A”, Section 50.7.8 “TC Register B” and Section 50.7.9 “TC Register C”. Section 50.7.14 “TC Extended Mode Register”: updated TRIGSRCB bit description.
08-Feb-16	Section 51. “Pulse Width Modulation Controller (PWM)” Number of fault inputs corrected to 8. Size of dead-time counter/generator corrected to 12 bits. Number of event lines corrected to 2. Number of comparison units corrected to 8. Updated Figure 51-1, “Pulse Width Modulation Controller Block Diagram”. Updated Section 51.6.2.2 “Comparator”. Updated Figure 51-33, “Leading-Edge Blanking”. Section 51.6.6.1 “Initialization”: modified “Enable of the interrupts...” list item. Added Section 51.6.6.4 “Changing the Update Period of Synchronous Channels”, Section 51.6.6.5 “Changing the Comparison Value and the Comparison Configuration” and Section 51.6.6.6 “Interrupt Sources”. Added reference to Section 51.5.4 “Fault Inputs” in register descriptions. Corrected PWM period formulas in Section 51.7.43 “PWM Channel Period Register”and Section 51.7.44 “PWM Channel Period Update Register”. Section 51.7.49 “PWM External Trigger Register” and Section 51.7.50 “PWM Leading-Edge Blanking Register”: corrected register index to 2. Section 51.7.50 “PWM Leading-Edge Blanking Register”: updated LEBDELAY bit description.
08-Feb-16	Section 52. “Analog Front-End Controller (AFEC)” Updated Section 52.6 “Functional Description”. Section 52.6.11 “Input Gain and Offset” changed AOFF configuration value. Corrected formula for offset values. Updated Section 52.6.12 “AFE Timings”. Section 52.6.18 “Register Write Protection”: added “AFEC Channel Differential Register” to the list of write-protected registers. Section 52.7.5 “AFEC Channel Sequence 2 Register”: corrected number of channels to 12. Section 52.7.13 “AFEC Interrupt Status Register”: defined EOCAL bit as ‘cleared on read’. Added sentence on write protection below the register table for: Section 52.7.20 “AFEC Channel Offset Compensation Register” Section 52.7.21 “AFEC Temperature Sensor Mode Register” Section 52.7.25 “AFEC Correction Select Register” Section 52.7.26 “AFEC Correction Values Register” Section 52.7.27 “AFEC Channel Error Correction Register” Section 52.7.20 “AFEC Channel Offset Compensation Register”: AOFF field modified to 10 bits (was 12 bits). Bits 10 and 11 now reserved.
08-Feb-16	Section 53. “Digital-to-Analog Converter Controller (DACC)” External Trigger mode changed to Trigger mode throughout. Removed references to ‘pipelined architecture’ and ‘pipeline’ throughout. Added information on Bypass mode in: - Section 53.1 “Description” - Section 53.6.4.4 “Bypass Mode” Updated Figure 53-1, “Block Diagram”. Updated Section 53.6.1 “Digital-to-Analog Conversion”. Added sentence on DACRDY. Changed ‘maximum conversion rate’ to ‘minimum conversion period’. Added Figure 53-2, “Conversion Sequence in Trigger Mode”and Figure 53-3, “Conversion Sequence in Free-running Mode”. Section 53.6.4.1 “Trigger Mode”: removed fragment ‘(either DATRG pin or timer counter events)’. Section 53.6.4.2 “Free-Running Mode”: added sentence on FIFO. Updated Figure 53-3, “Conversion Sequence in Free-running Mode”. Updated Section 53.6.4.3 “Max Speed Mode” and added Figure 53-4, “Conversion Sequence in Max Speed Mode”. Updated Section 53.6.4.4 “Bypass Mode”. Deleted section “DACC Timings”. Table 53-4 “Register Mapping”: modified reset value for DACC_MR. Section 53.7.2 “DACC Mode Register”: added bit ZERO (bit 5) and bit description. Section 53.7.3 “DACC Trigger Register”: bit description changed for TRGSEL bit. Removed bits ENDTX0, ENDTX1, TXBUFE0 and TXBUFE1 from Section 53.7.8 “DACC Interrupt Enable Register”, Section 53.7.9 “DACC Interrupt Disable Register”, Section 53.7.10 “DACC Interrupt Mask Register” and Section 53.7.11 “DACC Interrupt Status Register”.
	Section 55. “Integrity Check Monitor (ICM)” Section 55.5.2.2 “ICM Region Configuration Structure Member”: removed MRPROT field. Section 55.6.1 “ICM Configuration Register”: removed fields HAPROT and DAPROT; updated description DUALBUFF field
	Updated Section 58. “Electrical Characteristics”.
	Updated Section 59. “Mechanical Characteristics”.
	Added Section 60. “Schematic Checklist”.
	Added Section 63. “Errata”.

Table 9. SAM E70/S70/V70/V71 Datasheet Rev. 44003B – Revision History
Date	Changes
24-Feb-15	“Description”: updated details on PWM, 16-bit timers, RTC, RTT and Backup mode. Added note to QFN64 package on availability.
	“Features”: updated details on PWM. Added note to QFN64 package on availability.
	Section 1. “Configuration Summary” Table 1-1 “Configuration Summary”: Modifications made to Timer Counter Channels I/O, USART/UART, QSPI, SPI, USART SPI.
	Section 2. “Block Diagram”: added AHBP block. Added Backup RAM block. Removed TRACECTL. Changed block name to Serial Wire Debug/JTAG Boundary Scan (was JTAG and Serial Wire). Modified signal names to VREFP and VREFN (were ADVREFP and ADVREFN).
	Section 3. “Signal Description” Table 3-1 “Signal Description List“: corrected upper index for Two-wire Interface - TWIHS. Modified signal names to VREFP and VREFN (were ADVREFP and ADVREFN). In section FFPI, corrected upper index of signal PGMEN to ‘1’ and removed signal PGMCK.
	Section 5. “Package and Pinout” In all pinout tables, modified signal names to VREFP and VREFN (were ADVREFP and ADVREFN). Replaced tables “Pinout for 144-pin LQFP Package” and “Pinout for 144-pin LFBGA Package” with single Table 5-1 “144-lead Package Pinout“ and reworked the table. For Pin 110/PIOD: replaced TRACECTL with ’–’. Added notes to all signals in column ‘Alternate’ for details on selecting extra functions and system functions. Replaced tables “Pinout for 100-pin LQFP Package” and “Pinout for 100-ball TFBA Package”by single Table 5-2 “100-lead Package Pinout“ and reworked the table. Reworked table “Pinout for 64-pin LQFP Package” and renamed it to Table 5-3 “64-lead Package Pinout“.
	Section 6. “Power Considerations” Section 6.2 “Power Constraints”: updated constraint for VDDCORE, VDDPLL and VDDUTMIC. Section 6.2.1 “Power-up”: changed value of rising slope of VDDIO and VDDIN to 2.4V/ms. Section 6.2.2 “Power-down”: added detail on VDDCORE falling slope.
	Section 7. “Input/Output Lines” Section 7.1 “General-Purpose I/O Lines”: changed ODT to R_SERIAL in text and figure. Section 7.2.2 “Embedded Trace Module (ETM) Pins”; removed TRACECTL Section 7.5 “ERASE Pin”: added details on in-situ reprogrammability.
	Section 10. “Memories” Table 10-1 “TCM Configurations in Kbytes“: corrected column GPNVM Bit [8:7] by inverting values (0 first, 3 last). Table 10-4 “General-purpose Non volatile Memory Bits“: GPNVM bit 1: inverted 0 and 1 values. GPNVM bit 7–8: inverted all values for TCM configuration and added Note. Section 10.1.1 “Internal SRAM”: updated section. Section 10.1.2 “Tightly Coupled Memory (TCM) Interface”: added detail on enable/disable of ITCM/DTCM. Section 10.1.4 “Backup SRAM”: updated SRAM address. Removed detail on read/write accesses. Section 10.1.5 “Flash Memories”: added details on the attribute definitions for programming operations vs. fetch/read operations. Section 10.1.5.9 “Fast Flash Programming Interface”: removed ‘serial JTAG interface’.
	Section 11. “Event System” Table 11-1 “ Event Mapping List“: in row “Audio clock recovery from Ethernet’ changed the text in Description column.
	Section 13. “Peripherals” Table 13-1 “Peripheral Identifiers“: modfied content of column ‘Description’ for clarity. Section 13.2 “Peripheral Signal Multiplexing on I/O Lines”: corrected PIOC to PIOD for 100-pin version. Moved Section 13.3 “Peripheral Mapping to DMA” to Section 35.3 “DMA Controller Peripheral Connections”.
24-Feb-15	Section 15. “Debug and Test Features” Section 15.1 “Description”: removed references to JTAG Debug Port and JTAG-DP. Updated Figure 15-1 “Debug and Test Block Diagram”: added Cortex-M7, ETM and PCK3 blocks and trace pins. Renamed block ‘SWJ-DP’ to ‘SW-DP’. Table 15-1 “Debug and Test Signal List”: removed TRACECTL. Updated Figure 15-4 “Debug Architecture”. added ETM and Trace Port blocks. Removed TPIU. Section 15.6.5 “Serial Wire Debug Port (SW-DP) Pins”: removed all references to JTAG Debug Port and JTAG-DP. Section 15.6.6 “Embedded Trace Module (ETM) Pins”: removed TRACECTL from bullet points. Updated Section 15.6.7 “Flash Patch Breakpoint (FPB)” . Section 15.6.9.2 “Asynchronous Mode”: removed reference to JTAG Debug Port and JTAG debug mode.
	Section 16. “SAM-BA Boot Program” Section 16.6.4 “In Application Programming (IAP) Feature”: replaced software code example.
	Section 18. “Bus Matrix (MATRIX)” Table 18-3 “Master to Slave Access”: changed Master 4/Slave 4 access from possible (“x”) to not possble (‘-”) Table 18-4 “Register Mapping”: changed reset value for CCFG_SYSIO register. Section 18.12.7 “System I/O and CAN1 Configuration Register”: corrected typo in CAN1DMABA bit name. Section 18.11 “Register Write Protection”: replaced “The WPVS bit is automatically cleared after reading the MATRIX_WPSR” with “The WPVS flag is reset by writing the MATRIX_WPMR with the appropriate access key WPKEY” Section 18.12.10 “Write Protection Status Register”: in WPVS bit description, replaced two instances of “since the last read of the MATRIX_WPSR” with “since the last write of the MATRIX_WPMR”.
	Section 21. “Enhanced Embedded Flash Controller (EEFC)” Section 21.4.3.2 “Write Commands”: added information on DMA write accesses.
	Section 30. “Power Management Controller (PMC)” Section 30.9 “Asynchronous Partial Wake-up”: inserted new sub-section “Asynchronous Partial Wake-up in Wait Mode (SleepWalking)” to better describe SleepWalking. Section 30.10 “Free-Running Processor Clock”: removed reference to MCK.
	Section 31. “Parallel Input/Output Controller (PIO)” Section 31.2 “Embedded Characteristics”: added bullet on Programmable I/O Drive. Added Section 31.5.12 “Programmable I/O Drive”. Section 31.5.15.4 “Programming Sequence”: “With DMA”: in fifth step, replaced reference to BTCx with ‘DMA status flag to indicate that the buffer transfer is complete’ Table 31-5 “Register Mapping”: added PIO_DRIVER register at offset 0x0118 and added Section 31.6.49 “PIO I/O Drive Register”.
	Section 35. “DMA Controller (XDMAC)” Added Section 35.3 “DMA Controller Peripheral Connections”.
	Section 37. “USB High-Speed Interface (USBHS)” Table 37-1 “Description of USB Pipes/Endpoints“; corrected data in columns ‘DMA’ and ‘High Bandwidth’. Modified signal names to HSDM/DM and HSDP/DP in Figure 37-1 “USBHS Block Diagram” and Table 37-2 “Signal Description”. Updated descriptions. Removed Section 37.3.1 “Application Block Diagram” and Figures 37-2, 37-3 and 37-4. Removed Section 37.4.1 “I/O Lines”. Modified Section 37.5.3.3 “Device Detection”. Section 37.6.2 “General Status Register”, Section 37.6.3 “General Status Clear Register”, Section 37.6.4 “General Status Set Register”: removed bit VBUSRQ and bit description. Bit 9 now reserved in these registers.
24-Feb-15	Section 38. “Ethernet MAC (GMAC)” Section 38.8.13 “GMAC Interrupt Mask Register”: corrected general bit description (swapped definitions provided for 0: and 1:)
	Section 40. “Quad SPI Interface (QSPI)” Section 40.5.4 “Direct Memory Access Controller (DMA)”: added Note on 32-bit aligned DMA write accesses. Figure 40-9 “Instruction Transmission Flow Diagram”: modified text if TFRTYP = 0 Section 40.6.7 “Register Write Protection”: added Scrambling Mode Register and Scrambling Key Register to the list of registers that can be write-protected. Section 40.7.13 “QSPI Scrambling Mode Register” and Section 40.7.14 “QSPI Scrambling Key Register”: added “This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.”.
	Section 42. “Two-wire Interface (TWIHS)” Replaced all instances of ‘BTC’ with ‘DMA status flag’.
	Section 46. “MediaLB (MLB)” Table 46-2 “MLB External Signals”: modified signal names in this table and throughout the section.
	Section 47. “Controller Area Network (MCAN)” Figure 47-1 “MCAN Block Diagram”: added Note. Section 47.4.2 “Power Management”: added recommendations for CAN clock frequency. Added Section 47.4.4 “Address Configuration”.
	Section 48. “Timer Counter (TC)” Replaced occurrences of ‘quadrature decoder logic’with ‘quadrature decoder’ or ‘QDEC’ throughout the document. Section 48.7.14 “TC Extended Mode Register”: changed description for field TRIGSRCB for value 1.
	Section 49. “Pulse Width Modulation Controller (PWM)” Section 49.5.3 “Interrupt Sources”: removed the following sentence: “Note that it is not recommended to use the PWM interrupt line in Edge-sensitive mode.” “Method 3: Automatic write of duty-cycle values and automatic trigger of the update”: removed reference to non-existant field BTC. Modified Figure 49-28 “External PWM Reset Mode: Power Factor Correction Application”. Removed R_LIMIT and Zener diode from Figure 49-32 “Cycle-By-Cycle Duty Mode: LED String Control”.
	Section 50. “Analog Front-End Controller (AFEC)” In text and tables throughout this section, all occurrences of ADVREF have been modified to VREFP. Figure 50-1, “Analog Front-End Controller Block Diagram”: added 2nd DAC. Removed ADVREF; added VREFP and VREFN. Table 50-1 “AFEC Signal Description”: removed row with VDDANA. Added row with VREFN. Section 50.5 “Product Dependencies”: reorganized sub-sections. In Section 50.5.2 “Power Management”, added sentence on Sleep mode. Modified Section 50.5.1 “I/O Lines”. Removed section 50.5.3 Analog Inputs. Section 50.6.1 “Analog Front-End Conversion”: changed PRESCAL condition from ‘0’ to ‘1’ for frequency range fperipheral clock/2. Figure 50-7 “Analog Full Scale Ranges in Single-Ended/Differential Applications Versus Gain”: replaced all occurrences of VADVREF with VVREFP; replaced min ‘0’ value with VVREFN=0. Section 50.7.2 “AFEC Mode Register”: modified PRESCAL description.
24-Feb-15	Section 51. “Digital-to-Analog Converter (DACC)” Section 51.1 “Description”: removed information on refresh feature. Figure 51-1 “Block Diagram”: added VDDANA, VREFP and VREFN. Table 51-1 “DACC Signal Description”: added VREFP and VREFN to table. Section 51.2 “Embedded Characteristics”: removed bullet on refresh period. Added Section 51.5.1 “I/O Lines”. Section 51.6.3 “Analog Output Mode Selection”: corrected bit name for output modeselection to ‘DIFF’ from ‘ANA_MODE_SEL’ . Section 51.6.4 “Conversion Modes”: added details on enabling conversion modes. Removed bullet “Interpolated Mode”. Removed section 51.6.5 “Refresh Mode”. Updated Section 51.6.4.4 “Interpolation Mode”. Section 51.7.2 “DACC Mode Register”: removed field REFRESH and description. Bits 15:8 now reserved. Section 51.7.6 “DACC Channel Status Register”: modified DACRDYx bit descriptions. Section 51.7.11 “DACC Interrupt Status Register”: ENDTXx, TXBUFEx descriptions: corrected register name to ‘DACC_CDRx’ from ‘DACC _TCR or DACC_TNCR’.
	Section 52. “Analog Comparator Controller (ACC)” In text and in tables throughout this section, changed all occurrences of ADVREF to VREFP. Section 52.2 “Embedded Characteristics”: In bullet: “Four Voltage References...”, changed ADVREF to ‘External Voltage Reference’ Renamed Section 5. to “Signal Description” Removed Table 52-1 “List of External Analog Data Inputs” and note referring to this table.
	Section 53. “Integrity Check Monitor (ICM)” Section 53.1 “Description”: updated content. Renamed section “ICM SHA Engine” to “Using ICM as SHA Engine” and updated content. Added Section 53.5.4.1 “Settings for Simple SHA Calculation”. Section 53.5.2.2 “ICM Region Configuration Structure Member”: updated descriptions for RHIEN, DMIEN, BEIEN, WCIEN, ECIEN, SUIEN and MPROT. Section 53.6.1 “ICM Configuration Register”: updated descriptions for DAPROT and HAPROT. Section 53.6.3 “ICM Status Register”: updated descriptions for RAWRMDIS and RMDIS.
24-Feb-15	Section 55. “Advanced Encryption Standard (AES)” Section 55.4.5.2 “DMA Mode”: removed references to ‘BTC’ throughout.
	Section 56. “Electrical Characteristics” Table 56-1 “Absolute Maximum Ratings*“: added reference to Note 1 for 64-pin QFN package. Table 56-2 “DC Characteristics”: updated conditions for V_IL, V_IH, V_OH, V_OL, I_O, R_PULLUP, R_PULLDOWN, R_SERIAL.Added parameter Flash Active Current characteristics. Added parameter Static Current. Modified Note (1) below table. Table 56-3 “1.2V Voltage Regulator Characteristics”: removed note on VDDIO voltage at power-up (was Note 3). Updated note on VDDIO voltage value. Changed values of CD_OUT. Changed conditions for parameter t_START and CD_OUT value in Note 2. Table 56-4 “Core Power Supply Brownout Detector Characteristics”: updated all values. Changed Note 1. Table 56-6 “VDDIO Supply Monitor”: updated values for T_ACCURACY Table 56-9. “DC Flash Characteristics” moved to Table 56-2 “DC Characteristics”. Section 56.3.2.1 “Sleep Mode Conditions”: corrected number of WKUP pins. Added Section 56.3.6 “I/O Switching Power Consumption”. Table 56-21 “32 kHz RC Oscillator Characteristics”: changed max values to TBD for t_START, I_DDON and I_{DDON_STANDBY}. Table 56-25 “3 to 20 MHz Crystal Oscillator Characteristics”: for t_START and I_{DD_ON,}changed max values to TBD. Added parameter I_{DD._STANDBY.} Table 56-26 “Crystal Characteristics”: ESR: added new row with condition Fundamental at 3 MHz. Changed max values for 8 and 12 MHz. Table 56-29 “PLLA Characteristics”: changed max value of f_IN. Added parameter I_{DD_STDBY} Added Section 56.6 “PLLUSB Characteristics”> Updated section Section 56.7 “USB Transceiver Characteristics”. Moved Section 56.8 MediaLB to Section 56.8. Section 56.9 “AFE Characteristics”: changed numbering of sub-sections throughout. - Removed bullet on min and max data. - Changed all occurrences of ADVREFP to VREP, and of ADVREFN to VREFN throughout section. - Changed all occurrences of ADC to AFE, where relevant. - Modified Figure 56-11 “Single-ended Mode AFE” and Figure 56-12 “Differential Mode AFE”. - Table 56-36 “Power Supply Characteristics”: updated I_VDDIN conditions in and changed max values. Changed max values for I_VDDCORE. Removed Note 1 due to incorrect cross-reference. Added Note 3 on current consumption. - Table 56-38 “VREFP Electrical Characteristics”: changed min and max values for I_VREFP. - Table 56-46 “Single-ended Output Offset Error”: added note on voltage application. - Table 56-47 “Single-ended Static Electrical Characteristics”: added conditions and values. - Table 56-49 “Differential Static Electrical Characteristics”: changed min and max values. Added Section 56.10 “Analog Comparator Characteristics”. Section 56.12 “12-bit DAC Characteristics” - Added note to Table 56-59 “Analog Power Supply Characteristics”. Added new conditions to Table 56-62 “Static Performance Characteristics”. and updated min and max values for INL, DNL and Gain Error. Section 56.13 “Timings for Worst-Case Conditions” - Table 56-68 “I/O Characteristics”: new conditions and the corresponding max values added. - Section 56.13.2 “Embedded Flash Characteristics”: in Table 56-87 “AC Flash Characteristics” changed Full Chip Erase values. Replaced two “Embedded Flash Wait State” tables with single Table 56-88 “Embedded Flash Wait State at 105°C“
	Section 56.14 “Timings for STH Conditions” - Table 56-92 “I/O Characteristics”: new conditions and the corresponding max values added. - Section 56.14.2 “Embedded Flash Characteristics”: replaced two “Embedded Flash Wait State” tables with single Table 56-112 “Embedded Flash Wait State at 105°C“
	Section 57. “Mechanical Characteristics” Deleted Section 57.6 “64-lead QFN Wettable Flanks Package”.
	Section 59. “Ordering Information”: updated ordering codes by appending trailing ‘T’. Removed Note 1 and cross-references. Changed conditioning to Tape & Reel.

Table 10. SAM E70/S70/V70/V71 Datasheet Rev. 44003A – Revision History
Date	Changes
15-Oct-13	First issue