Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0
0x00 SMC_SETUP0 7:0     NWE_SETUP[5:0]
15:8     NCS_WR_SETUP[5:0]
23:16     NRD_SETUP[5:0]
31:24     NCS_RD_SETUP[5:0]
0x04 SMC_PULSE0 7:0   NWE_PULSE[6:0]
15:8   NCS_WR_PULSE[6:0]
23:16   NRD_PULSE[6:0]
31:24   NCS_RD_PULSE[6:0]
0x08 SMC_CYCLE0 7:0 NWE_CYCLE[7:0]
15:8               NWE_CYCLE[8]
23:16 NRD_CYCLE[7:0]
31:24               NRD_CYCLE[8]
0x0C SMC_MODE0 7:0     EXNW_MODE[1:0]     WRITE_MODE READ_MODE
15:8       DBW       BAT
23:16       TDF_MODE TDF_CYCLES[3:0]
31:24     PS[1:0]       PMEN
0x10 SMC_SETUP1 7:0     NWE_SETUP[5:0]
15:8     NCS_WR_SETUP[5:0]
23:16     NRD_SETUP[5:0]
31:24     NCS_RD_SETUP[5:0]
0x14 SMC_PULSE1 7:0   NWE_PULSE[6:0]
15:8   NCS_WR_PULSE[6:0]
23:16   NRD_PULSE[6:0]
31:24   NCS_RD_PULSE[6:0]
0x18 SMC_CYCLE1 7:0 NWE_CYCLE[7:0]
15:8               NWE_CYCLE[8]
23:16 NRD_CYCLE[7:0]
31:24               NRD_CYCLE[8]
0x1C SMC_MODE1 7:0     EXNW_MODE[1:0]     WRITE_MODE READ_MODE
15:8       DBW       BAT
23:16       TDF_MODE TDF_CYCLES[3:0]
31:24     PS[1:0]       PMEN
0x20 SMC_SETUP2 7:0     NWE_SETUP[5:0]
15:8     NCS_WR_SETUP[5:0]
23:16     NRD_SETUP[5:0]
31:24     NCS_RD_SETUP[5:0]
0x24 SMC_PULSE2 7:0   NWE_PULSE[6:0]
15:8   NCS_WR_PULSE[6:0]
23:16   NRD_PULSE[6:0]
31:24   NCS_RD_PULSE[6:0]
0x28 SMC_CYCLE2 7:0 NWE_CYCLE[7:0]
15:8               NWE_CYCLE[8]
23:16 NRD_CYCLE[7:0]
31:24               NRD_CYCLE[8]
0x2C SMC_MODE2 7:0     EXNW_MODE[1:0]     WRITE_MODE READ_MODE
15:8       DBW       BAT
23:16       TDF_MODE TDF_CYCLES[3:0]
31:24     PS[1:0]       PMEN
0x30 SMC_SETUP3 7:0     NWE_SETUP[5:0]
15:8     NCS_WR_SETUP[5:0]
23:16     NRD_SETUP[5:0]
31:24     NCS_RD_SETUP[5:0]
0x34 SMC_PULSE3 7:0   NWE_PULSE[6:0]
15:8   NCS_WR_PULSE[6:0]
23:16   NRD_PULSE[6:0]
31:24   NCS_RD_PULSE[6:0]
0x38 SMC_CYCLE3 7:0 NWE_CYCLE[7:0]
15:8               NWE_CYCLE[8]
23:16 NRD_CYCLE[7:0]
31:24               NRD_CYCLE[8]
0x3C SMC_MODE3 7:0     EXNW_MODE[1:0]     WRITE_MODE READ_MODE
15:8       DBW       BAT
23:16       TDF_MODE TDF_CYCLES[3:0]
31:24     PS[1:0]       PMEN

0x40

...

0x7F

Reserved                  
0x80 SMC_OCMS 7:0               SMSE
15:8         CS3SE CS2SE CS1SE CS0SE
23:16                
31:24                
0x84 SMC_KEY1 7:0 KEY1[7:0]
15:8 KEY1[15:8]
23:16 KEY1[23:16]
31:24 KEY1[31:24]
0x88 SMC_KEY2 7:0 KEY2[7:0]
15:8 KEY2[15:8]
23:16 KEY2[23:16]
31:24 KEY2[31:24]

0x8C

...

0xE3

Reserved                  
0xE4 SMC_WPMR 7:0               WPEN
15:8 WPKEY[7:0]
23:16 WPKEY[15:8]
31:24 WPKEY[23:16]
0xE8 SMC_WPSR 7:0               WPVS
15:8 WPVSRC[7:0]
23:16 WPVSRC[15:8]
31:24