SDRAMC_TR

SDRAMC Refresh Timer Register

  0x04 32 Read/Write 0x00000000  

SDRAMC Refresh Timer Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          COUNT[11:8]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  COUNT[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 11:0 – COUNT[11:0]: SDRAMC Refresh Timer Count

SDRAMC Refresh Timer Count

This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562 (15.625 μs x 100 MHz) or 781 (7.81 μs x 100 MHz).

To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.