Master Transfer

  1. 1.Read the XDMAC_GS register to choose a free channel.
  2. 2.Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register.
  3. 3.Build a linked list of transfer descriptors in memory. The descriptor view is programmable on a per descriptor basis. The linked list items structure must be word aligned. MBR_UBC.NDE must be configured to 0 in the last descriptor to terminate the list.
  4. 4.Configure field NDA in the XDMAC Channel x Next Descriptor Address Register (XDMAC_CNDAx) with the first descriptor address and bit XDMAC_CNDAx.NDAIF with the master interface identifier.
  5. 5.Configure the XDMAC_CNDCx register:
    1. a.Set XDMAC_CNDCx.NDE to enable the descriptor fetch.
    2. b.Set XDMAC_CNDCx.NDSUP to update the source address at the descriptor fetch time, otherwise clear this bit.
    3. c.Set XDMAC_CNDCx.NDDUP to update the destination address at the descriptor fetch time, otherwise clear this bit.
    4. d.Configure XDMAC_CNDCx.NDVIEW to define the length of the first descriptor.
  6. 6.Enable the End of Linked List interrupt by writing a ‘1’ to XDMAC_CIEx.LIE.
  7. 7.Enable channel x by writing a ‘1’ to XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware.
  8. 8.Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.
Parent topic: XDMAC Transfer Software Operation