PWM_IMR2

PWM Interrupt Mask Register 2

  0x3C 32 Read-only 0x00000000  
Parent topic: Register Summary

PWM Interrupt Mask Register 2

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
          UNRE     WRDY  
Access          R     R  
Reset          0     0  

Bit 0 – WRDY: Write Ready for Synchronous Channels Update Interrupt Mask

Write Ready for Synchronous Channels Update Interrupt Mask

Bit 3 – UNRE: Synchronous Channels Update Underrun Error Interrupt Mask

Synchronous Channels Update Underrun Error Interrupt Mask

Bits 8, 9, 10, 11, 12, 13, 14, 15 – CMPMx: Comparison x Match Interrupt Mask

Comparison x Match Interrupt Mask

Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx: Comparison x Update Interrupt Mask

Comparison x Update Interrupt Mask