AFEC_SHMR

AFEC Sample & Hold Mode Register

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

  0xA0 32 Read/Write 0x00000000  
Parent topic: Register Summary

AFEC Sample & Hold Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          DUAL11 DUAL10 DUAL9 DUAL8  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  DUAL7 DUAL6 DUAL5 DUAL4 DUAL3 DUAL2 DUAL1 DUAL0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – DUALx: Dual Sample & Hold for Channel x

Dual Sample & Hold for Channel x

ValueDescription
0

Single Sample-and-Hold mode.
1

Dual Sample-and-Hold mode.