Device Endpoint Interrupt Set Register (Control, Bulk, Interrupt Endpoints)
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NBUSYBKS | |||||||||
| Access | |||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHORTPACKETS | STALLEDIS | OVERFIS | NAKINIS | NAKOUTIS | RXSTPIS | RXOUTIS | TXINIS | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Transmitted IN Data Interrupt Set
Received OUT Data Interrupt Set
Received SETUP Interrupt Set
NAKed OUT Interrupt Set
NAKed IN Interrupt Set
Overflow Interrupt Set
STALLed Interrupt Set
Short Packet Interrupt Set
Number of Busy Banks Interrupt Set