The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by RSTC_MR.ERSTL. This assertion duration, named External Reset Length, lasts 2(ERSTL+1) SLCK cycles. This gives the approximate duration of an assertion between 60 μs and 2 seconds. Note that ERSTL at ‘0’ defines a two-cycle duration for the NRST pulse.
This feature allows the RSTC to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.
RSTC_MR is backed up, making it possible to use the value of ERSTL to shape the system powerup reset for devices requiring a longer startup time than that of the MCU.