TC_QIDR

TC QDEC Interrupt Disable Register

  0xCC 32 Write-only –  
Parent topic: Register Summary

TC QDEC Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          MPE QERR DIRCHG IDX  
Access          W W W W  
Reset          – – – –  

Bit 0 – IDX: Index

Index

ValueDescription
0 No effect.
1 Disables the interrupt when a rising edge occurs on IDX input.

Bit 1 – DIRCHG: Direction Change

Direction Change

ValueDescription
0 No effect.
1 Disables the interrupt when a change on rotation direction is detected.

Bit 2 – QERR: Quadrature Error

Quadrature Error

ValueDescription
0 No effect.
1 Disables the interrupt when a quadrature error occurs on PHA, PHB.

Bit 3 – MPE: Consecutive Missing Pulse Error

Consecutive Missing Pulse Error

ValueDescription
0 No effect.
1 Disables the interrupt when an occurrence of MAXCMP consecutive missing pulses has been detected.