XDMAC_GRWS

XDMAC Global Channel Read Write Suspend Register

  0x30 32 Write-only –  

XDMAC Global Channel Read Write Suspend Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  RWS23 RWS22 RWS21 RWS20 RWS19 RWS18 RWS17 RWS16  
Access  W W W W W W W W  
Reset   
Bit  15 14 13 12 11 10 9 8  
  RWS15 RWS14 RWS13 RWS12 RWS11 RWS10 RWS9 RWS8  
Access  W W W W W W W W  
Reset   
Bit  7 6 5 4 3 2 1 0  
  RWS7 RWS6 RWS5 RWS4 RWS3 RWS2 RWS1 RWS0  
Access  W W W W W W W W  
Reset   

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – RWSx: XDMAC Channel x Read Write Suspend

XDMAC Channel x Read Write Suspend

ValueDescription
0

No effect.

1

Read and write requests are suspended.