AFEC_CHER

AFEC Channel Enable Register

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

  0x14 32 Write-only –  
Parent topic: Register Summary

AFEC Channel Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          CH11 CH10 CH9 CH8  
Access          W W W W  
Reset          – – – –  
Bit  7 6 5 4 3 2 1 0  
  CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0  
Access  W W W W W W W W  
Reset  – – – – – – – –  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHx: Channel x Enable

Channel x Enable

If AFEC_MR.USEQ = 1, CHx corresponds to the xth channel of the sequence described in AFEC_SEQ1R, AFEC_SEQ2R.
ValueDescription
0

No effect.
1

Enables the corresponding channel.