US_MR

USART Mode Register

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

For SPI configuration, see “USART Mode Register (SPI_MODE)”.

  0x0004 32 Read/Write 0x0  

USART Mode Register

Bit  31 30 29 28 27 26 25 24  
  ONEBIT MODSYNC MAN FILTER   MAX_ITERATION[2:0]  
Access                   
Reset  0 0 0 0   0 0 0  
Bit  23 22 21 20 19 18 17 16  
  INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CHMODE[1:0] NBSTOP[1:0] PAR[2:0] SYNC  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CHRL[1:0] USCLKS[1:0] USART_MODE[3:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 3:0 – USART_MODE[3:0]: USART Mode of Operation

USART Mode of Operation

ValueNameDescription
0x0 NORMAL

Normal mode

0x1 RS485

RS485

0x2 HW_HANDSHAKING

Hardware Handshaking

0x3 MODEM

Modem

0x4 IS07816_T_0

IS07816 Protocol: T = 0

0x6 IS07816_T_1

IS07816 Protocol: T = 1

0x8 IRDA

IrDA

0x9 LON

LON

0xA LIN_MASTER

LIN Master mode

0xB LIN_SLAVE

LIN Slave mode

0xE SPI_MASTER

SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)

0xF SPI_SLAVE

SPI Slave mode

Bits 5:4 – USCLKS[1:0]: Clock Selection

Clock Selection

ValueNameDescription
0 MCK

Peripheral clock is selected

1 DIV

Peripheral clock divided (DIV=DIV=8) is selected

2 PCK

PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.

2

Reserved

3 SCK

Serial clock (SCK) is selected

Bits 7:6 – CHRL[1:0]: Character Length

Character Length

ValueNameDescription
0 5_BIT

Character length is 5 bits

1 6_BIT

Character length is 6 bits

2 7_BIT

Character length is 7 bits

3 8_BIT

Character length is 8 bits

Bit 8 – SYNC: Synchronous Mode Select

Synchronous Mode Select

ValueDescription
0

USART operates in Asynchronous mode.

1

USART operates in Synchronous mode.

Bits 11:9 – PAR[2:0]: Parity Type

Parity Type

ValueNameDescription
0 EVEN

Even parity

1 ODD

Odd parity

2 SPACE

Parity forced to 0 (Space)

3 MARK

Parity forced to 1 (Mark)

4 NO

No parity

6 MULTIDROP

Multidrop mode

Bits 13:12 – NBSTOP[1:0]: Number of Stop Bits

Number of Stop Bits

ValueNameDescription
0 1_BIT

1 stop bit

1 1_5_BIT

1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)

2 2_BIT

2 stop bits

Bits 15:14 – CHMODE[1:0]: Channel Mode

Channel Mode

ValueNameDescription
0 NORMAL

Normal mode

1 AUTOMATIC

Automatic Echo. Receiver input is connected to the TXD pin.

2 LOCAL_LOOPBACK

Local Loopback. Transmitter output is connected to the Receiver Input.

3 REMOTE_LOOPBACK

Remote Loopback. RXD pin is internally connected to the TXD pin.

Bit 16 – MSBF: Bit Order

Bit Order

ValueDescription
0

Least significant bit is sent/received first.

1

Most significant bit is sent/received first.

Bit 17 – MODE9: 9-bit Character Length

9-bit Character Length

ValueDescription
0

CHRL defines character length.

1

9-bit character length.

Bit 18 – CLKO: Clock Output Select

Clock Output Select

ValueDescription
0

The USART does not drive the SCK pin.

1

The USART drives the SCK pin if USCLKS does not select the external clock SCK.

Bit 19 – OVER: Oversampling Mode

Oversampling Mode

ValueDescription
0

16X Oversampling

1

8X Oversampling

Bit 20 – INACK: Inhibit Non Acknowledge

Inhibit Non Acknowledge

ValueDescription
0

The NACK is generated.

1

The NACK is not generated.

Bit 21 – DSNACK: Disable Successive NACK

Disable Successive NACK

ValueDescription
0

NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).

1

Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is asserted.

Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared.

Bit 23 – INVDATA: Inverted Data

Inverted Data

ValueDescription
0

The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the same as RXD line. Normal mode of operation.

1

The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of operation, useful for contactless card application. To be used with configuration bit MSBF.

Bit 22 – VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter

Variable Synchronization of Command/Data Sync Start Frame Delimiter

ValueDescription
0

User defined configuration of command or data sync field depending on MODSYNC value.

1

The sync field is updated when a character is written into US_THR.

Bits 26:24 – MAX_ITERATION[2:0]: Maximum Number of Automatic Iteration

Maximum Number of Automatic Iteration

ValueDescription
0–7

Defines the maximum number of iterations in ISO7816 mode, protocol T = 0.

Bit 28 – FILTER: Receive Line Filter

Receive Line Filter

ValueDescription
0

The USART does not filter the receive line.

1

The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

Bit 29 – MAN: Manchester Encoder/Decoder Enable

Manchester Encoder/Decoder Enable

ValueDescription
0

Manchester encoder/decoder are disabled.

1

Manchester encoder/decoder are enabled.

Bit 30 – MODSYNC: Manchester Synchronization Mode

Manchester Synchronization Mode

ValueDescription
0

The Manchester start bit is a 0 to 1 transition

1

The Manchester start bit is a 1 to 0 transition.

Bit 31 – ONEBIT: Start Frame Delimiter Selector

Start Frame Delimiter Selector

ValueDescription
0

Start frame delimiter is COMMAND or DATA SYNC.

1

Start frame delimiter is one bit.