DACC_ISR

DACC Interrupt Status Register

  0x30 32 Read-only 0x00000000  
Parent topic: Register Summary

DACC Interrupt Status Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
      EOC1 EOC0     TXRDY1 TXRDY0  
Access      R R     R R  
Reset      0 0     0 0  

Bits 0, 1 – TXRDYx: Transmit Ready Interrupt Flag of channel x

Transmit Ready Interrupt Flag of channel x

ValueDescription
0

DACC is not ready to accept new conversion requests.
1

DACC is ready to accept new conversion requests.

Bits 4, 5 – EOCx: End of Conversion Interrupt Flag of channel x

End of Conversion Interrupt Flag of channel x

ValueDescription
0

No conversion has been performed since the last read of DACC_ISR.
1

At least one conversion has been performed since the last read of DACC_ISR.