SUPC_SR

Supply Controller Status Register

Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR.

This register is located in the VDDIO domain.

  0x14 32 Read-only 0x00000000  

Supply Controller Status Register

Bit  31 30 29 28 27 26 25 24  
      WKUPIS[13:8]  
Access      R R R R R R  
Reset      0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  WKUPIS[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
    LPDBCS1 LPDBCS0            
Access    R R            
Reset    0 0            
Bit  7 6 5 4 3 2 1 0  
  OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS    
Access  R R R R R R R    
Reset  0 0 0 0 0 0 0    

Bit 1 – WKUPS: WKUP Wakeup Status (cleared on read)

WKUP Wakeup Status (cleared on read)

ValueDescription
0

(NO): No wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.

1

(PRESENT): At least one wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.

Bit 2 – SMWS: Supply Monitor Detection Wakeup Status (cleared on read)

Supply Monitor Detection Wakeup Status (cleared on read)

ValueDescription
0

(NO): No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR.

1

(PRESENT): At least one wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR.

Bit 3 – BODRSTS: Brownout Detector Reset Status (cleared on read)

Brownout Detector Reset Status (cleared on read)

When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell. The rising edge event occurs only when there is a voltage transition below the threshold.

ValueDescription
0

(NO): No core brownout rising edge event has been detected since the last read of the SUPC_SR.

1

(PRESENT): At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.

Bit 4 – SMRSTS: Supply Monitor Reset Status (cleared on read)

Supply Monitor Reset Status (cleared on read)

ValueDescription
0

(NO): No supply monitor detection has generated a core reset since the last read of the SUPC_SR.

1

(PRESENT): At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.

Bit 5 – SMS: Supply Monitor Status (cleared on read)

Supply Monitor Status (cleared on read)

ValueDescription
0

(NO): No supply monitor detection since the last read of SUPC_SR.

1

(PRESENT): At least one supply monitor detection since the last read of SUPC_SR.

Bit 6 – SMOS: Supply Monitor Output Status

Supply Monitor Output Status

ValueDescription
0

(HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement.

1

(LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement.

Bit 7 – OSCSEL: 32-kHz Oscillator Selection Status

32-kHz Oscillator Selection Status

ValueDescription
0

(RC): The slow clock, SLCK, is generated by the slow RC oscillator.

1

(CRYST): The slow clock, SLCK, is generated by the 32.768 kHz crystal oscillator.

Bit 13 – LPDBCS0: Low-power Debouncer Wakeup Status on WKUP0 (cleared on read)

Low-power Debouncer Wakeup Status on WKUP0 (cleared on read)

ValueDescription
0

(NO): No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.

1

(PRESENT): At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.

Bit 14 – LPDBCS1: Low-power Debouncer Wakeup Status on WKUP1 (cleared on read)

Low-power Debouncer Wakeup Status on WKUP1 (cleared on read)

ValueDescription
0

(NO): No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.

1

(PRESENT): At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.

Bits 29:16 – WKUPIS[13:0]: WKUPx ('x' = 0-13) Input Status (cleared on read)

WKUPx ('x' = 0-13) Input Status (cleared on read)

ValueDescription
0

(DIS): The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event.

1

(EN): The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR.