Reinforced Safety Watchdog Timer Status Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WDUNF | |||||||||
| Access | |||||||||
| Reset | 0 |
Watchdog Underflow
| Value | Description |
|---|---|
| 0 | No watchdog underflow occurred since the last read of RSWDT_SR. |
| 1 | At least one watchdog underflow occurred since the last read of RSWDT_SR. |