Host Pipe x Disable Register (Control, Bulk Pipes)
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPIMRx.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PFREEZEC | PDISHDMAC | ||||||||
| Access | |||||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOCONC | NBUSYBKEC | ||||||||
| Access | |||||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHORTPACKETIEC | RXSTALLDEC | OVERFIEC | NAKEDEC | PERREC | TXSTPEC | TXOUTEC | RXINEC | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Received IN Data Interrupt Disable
Transmitted OUT Data Interrupt Disable
Transmitted SETUP Interrupt Disable
Pipe Error Interrupt Disable
NAKed Interrupt Disable
Overflow Interrupt Disable
Received STALLed Interrupt Disable
Short Packet Interrupt Disable
Number of Busy Banks Disable
FIFO Control Disable
Pipe Interrupts Disable HDMA Request Disable
Pipe Freeze Disable