TWIHS_IDR

TWIHS Interrupt Disable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

  0x28 32 Write-only –  
Parent topic: Register Summary

TWIHS Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          EOSACC SCL_WS ARBLST NACK  
Access          W W W W  
Reset          – – – –  
Bit  7 6 5 4 3 2 1 0  
  UNRE OVRE GACC SVACC   TXRDY RXRDY TXCOMP  
Access  W W W W   W W W  
Reset  – – – –   – – –  

Bit 0 – TXCOMP: Transmission Completed Interrupt Disable

Transmission Completed Interrupt Disable

Bit 1 – RXRDY: Receive Holding Register Ready Interrupt Disable

Receive Holding Register Ready Interrupt Disable

Bit 2 – TXRDY: Transmit Holding Register Ready Interrupt Disable

Transmit Holding Register Ready Interrupt Disable

Bit 4 – SVACC: Slave Access Interrupt Disable

Slave Access Interrupt Disable

Bit 5 – GACC: General Call Access Interrupt Disable

General Call Access Interrupt Disable

Bit 6 – OVRE: Overrun Error Interrupt Disable

Overrun Error Interrupt Disable

Bit 7 – UNRE: Underrun Error Interrupt Disable

Underrun Error Interrupt Disable

Bit 8 – NACK: Not Acknowledge Interrupt Disable

Not Acknowledge Interrupt Disable

Bit 9 – ARBLST: Arbitration Lost Interrupt Disable

Arbitration Lost Interrupt Disable

Bit 10 – SCL_WS: Clock Wait State Interrupt Disable

Clock Wait State Interrupt Disable

Bit 11 – EOSACC: End Of Slave Access Interrupt Disable

End Of Slave Access Interrupt Disable