GMAC_TSR

GMAC Transmit Status Register

  0x014 32 - 0x00000000  

GMAC Transmit Status Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                HRESP  
Access                R/W  
Reset                0  
Bit  7 6 5 4 3 2 1 0  
      TXCOMP TFC TXGO RLE COL UBR  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  

Bit 0 – UBR: Used Bit Read

Used Bit Read

This bit is set when a transmit buffer descriptor is read with its used bit set.

This bit is cleared by writing a '1' to it.

Bit 1 – COL: Collision Occurred

Collision Occurred

When operating in 10/100Mbps mode, this bit is set by the assertion of either a collision or a late collision.

This bit is cleared by writing a '1' to it.

Bit 2 – RLE: Retry Limit Exceeded

Retry Limit Exceeded

This bit is cleared by writing a '1' to it.

Bit 3 – TXGO: Transmit Go

Transmit Go

This bit is '1' when transmit is active. When using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description.

Bit 4 – TFC: Transmit Frame Corruption Due to AHB Error

Transmit Frame Corruption Due to AHB Error

This bit is set when an error occurs during reading transmit frame from the AHB. Error causes include HRESP errors and buffers exhausted mid frame. (If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted).

In DMA packet buffer mode, this bit is also set if a single frame is too large for the configured packet buffer memory size.

This bit is cleared by writing a '1' to it.

Bit 5 – TXCOMP: Transmit Complete

Transmit Complete

Set when a frame has been transmitted.

This bit is cleared by writing a '1' to it.

Bit 8 – HRESP: HRESP Not OK

HRESP Not OK

Set when the DMA block sees HRESP not OK.

This bit is cleared by writing a '1' to it.