USBHS_HSTPIPICRx

Host Pipe x Clear Register (Control, Bulk Pipes)

This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.

For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Clears the corresponding bit in USBHS_HSTPIPISRx.

  0x0560 + x*0x04 [x=0..9] 32 Read/Write 0   10 x
Parent topic: Register Summary

Host Pipe x Clear Register (Control, Bulk Pipes)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  SHORTPACKETIC RXSTALLDIC OVERFIC NAKEDIC   TXSTPIC TXOUTIC RXINIC  
Access                   
Reset  0 0 0 0   0 0 0  

Bit 0 – RXINIC: Received IN Data Interrupt Clear

Received IN Data Interrupt Clear

Bit 1 – TXOUTIC: Transmitted OUT Data Interrupt Clear

Transmitted OUT Data Interrupt Clear

Bit 2 – TXSTPIC: Transmitted SETUP Interrupt Clear

Transmitted SETUP Interrupt Clear

Bit 4 – NAKEDIC: NAKed Interrupt Clear

NAKed Interrupt Clear

Bit 5 – OVERFIC: Overflow Interrupt Clear

Overflow Interrupt Clear

Bit 6 – RXSTALLDIC: Received STALLed Interrupt Clear

Received STALLed Interrupt Clear

Bit 7 – SHORTPACKETIC: Short Packet Interrupt Clear

Short Packet Interrupt Clear