TWIHS Master Mode Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DADR[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MREAD | IADRSZ[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Internal Device Address Size
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No internal device address |
| 1 | 1_BYTE | One-byte internal device address |
| 2 | 2_BYTE | Two-byte internal device address |
| 3 | 3_BYTE | Three-byte internal device address |
Master Read Direction
| Value | Description |
|---|---|
| 0 | Master write direction. |
| 1 | Master read direction. |
Device Address
The device address is used to access slave devices in Read or Write mode. These bits are only used in Master mode.