XDMAC_GIE

XDMAC Global Interrupt Enable Register

  0x0C 32 Write-only –  
Parent topic: Register Summary

XDMAC Global Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16  
Access  W W W W W W W W  
Reset  – – – – – – – –  
Bit  15 14 13 12 11 10 9 8  
  IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8  
Access  W W W W W W W W  
Reset  – – – – – – – –  
Bit  7 6 5 4 3 2 1 0  
  IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0  
Access  W W W W W W W W  
Reset  – – – – – – – –  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – IE: XDMAC Channel x Interrupt Enable

XDMAC Channel x Interrupt Enable

ValueDescription
0

This bit has no effect. The Channel x Interrupt Mask bit (XDMAC_GIM.IMx) is not modified.
1

The corresponding mask bit is set. The XDMAC Channel x Interrupt Status register (XDMAC_GIS) can generate an interrupt.