PWM Channel Period Update Register
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform period.
Only the first 16 bits (channel counter size) are significant.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CPRDUPD[23:16] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CPRDUPD[15:8] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CPRDUPD[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | – |
Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated:
– By using the PWM peripheral clock divided by a given prescaler value “X”
(where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula is:
– By using the PWM peripheral clock divided by a given prescaler value “X”
(see above) and by either the DIVA or the DIVB divider. The formula becomes,
respectively:
– By using the PWM peripheral clock divided by a given prescaler value “X”
(where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula is:
– By using the PWM peripheral clock divided by a given prescaler value “X”
(see above) and by either the DIVA or the DIVB divider. The formula becomes,
respectively: