QSPI Mode Register
This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DLYCS[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DLYBCT[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NBBITS[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TAMPCLR | CSMODE[1:0] | WDRBT | LLB | SMM | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Serial Memory Mode
0 (SPI): The QSPI is in SPI mode.
1 (MEMORY): The QSPI is in Serial Memory mode.
Local Loopback Enable
0 (DISABLED): Local loopback path disabled.
1 (ENABLED): Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in SPI mode only. (MISO is internally connected on MOSI).
Wait Data Read Before Transfer
0 (DISABLED): No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.
1 (ENABLED): In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
The QSPI in SPI mode does not support the Wait Data Read Before Transfer feature, the WDRBT bit in the SPI Mode Register (SPI_MR) must be ignored.Chip Select Mode
The CSMODE field determines how the chip select is deasserted
Value | Name | Description |
---|---|---|
0 | NOT_RELOADED | The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. |
1 | LASTXFER | The chip select is deasserted when the bit LASTXFER is written to ‘1’ and the character written in QSPI_TDR.TD has been transferred. |
2 | SYSTEMATICALLY | The chip select is deasserted systematically after each transfer. |
Tamper Clear Enable
Value | Description |
---|---|
0 |
A tamper detection event has no effect on QSPI scrambling keys. |
1 |
A tamper detection event immediately clears QSPI scrambling keys. |
Number Of Bits Per Transfer
Value | Name | Description |
---|---|---|
0 | 8_BIT | 8 bits for transfer |
8 | 16_BIT | 16 bits for transfer |
Minimum Inactive QCS Delay
This field defines the minimum delay between the deactivation and the activation of QCS. The DLYCS time guarantees the slave minimum deselect time.
If DLYCS written to ‘0’, one peripheral clock period is inserted by default.
Otherwise, the following equation determines the delay:
DLYCS = Minimum inactive × fperipheral clock
Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT is written to ‘0’, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. In Serial Memory mode (SMM = 1), DLYBCT must be written to ‘0’ and no delay is inserted.
Otherwise, the following equation determines the delay:
DLYBCT = (Delay Between Consecutive Transfers × fperipheral clock) / 32