GMAC Interrupt Disable Register
This register is write-only and will always return zero.
The following values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
TSUTIMCMP | WOL | RXLPISBC | SRI | PDRSFT | PDRQFT | ||||
Access | W | W | R | W | W | W | |||
Reset | – | – | – | – | – | – |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PDRSFR | PDRQFR | SFT | DRQFT | SFR | DRQFR | ||||
Access | W | W | W | W | W | W | |||
Reset | – | – | – | – | – | – |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
EXINT | PFTR | PTZ | PFNZ | HRESP | ROVR | ||||
Access | W | W | W | W | W | W | |||
Reset | – | – | – | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TCOMP | TFC | RLEX | TUR | TXUBR | RXUBR | RCOMP | MFS | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Management Frame Sent
Receive Complete
RX Used Bit Read
TX Used Bit Read
Transmit Underrun
Retry Limit Exceeded or Late Collision
Transmit Frame Corruption Due to AHB Error
Transmit Complete
Receive Overrun
HRESP Not OK
Pause Frame with Non-zero Pause Quantum Received
Pause Time Zero
Pause Frame Transmitted
External Interrupt
PTP Delay Request Frame Received
PTP Sync Frame Received
PTP Delay Request Frame Transmitted
PTP Sync Frame Transmitted
PDelay Request Frame Received
PDelay Response Frame Received
PDelay Request Frame Transmitted
PDelay Response Frame Transmitted
TSU Seconds Register Increment
Receive LPI indication Status Bit Change
Receive LPI indication status bit change.
Cleared on read.
Wake On LAN
TSU Timer Comparison